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| 型號： | CY7C1314BV18-167BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 512K X 36 QDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大?。?/td> | 262K |
| 代理商： | CY7C1314BV18-167BZC |
PRELIMINARY
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Document #: 38-05619 Rev. **
Page 12 of 23
Switching Characteristics
Over the Operating Range
[15,16]
Cypress
Parameter
t
POWER
t
CYC
t
KH
t
KL
t
KHKH
Consortium
Parameter
Description
250 MHz
Min.
1
4.0
1.6
1.6
1.8
200 MHz
Min.
1
5.0
2.0
2.0
2.2
167 MHz
Min.
1
6.0
2.4
2.4
2.7
Unit
ms
ns
ns
ns
ns
Max.
Max.
Max.
V
DD
(Typical) to the first Access
[19]
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising
edge to rising edge)
t
KHKH
t
KHKL
t
KLKH
t
KHKH
6.3
–
–
–
7.9
–
–
–
7.9
–
–
–
t
KHCH
t
KHCH
0.0
1.8
0.0
2.2
0.0
2.7
ns
Set-up Times
t
SA
t
SC
t
SCDDR
t
SA
t
SC
t
SC
Address Set-up to K Clock Rise
Control Set-up to Clock (K, K) Rise (RPS, WPS)
Double Data Rate Control Set-up to Clock (K,
K) Rise (BWS
0
, BWS
1
, BWS
3
, BWS
4
)
D
[X:0]
Set-up to Clock (K and K) Rise
0.35
0.5
0.35
–
–
–
0.4
0.6
0.4
–
–
–
0.5
0.5
0.5
–
–
–
ns
ns
ns
t
SD
Hold Times
t
HA
t
HC
t
SD
0.35
–
0.4
–
0.5
–
ns
t
HA
t
HC
Address Hold after Clock (K and K) Rise
Control Hold after Clock (K and K) Rise (RPS,
WPS)
Double Data Rate Control Hold after Clock (K
and K) Rise (BWS
0
, BWS
1
, BWS
3
, BWS
4
)
D
[X:0]
Hold after Clock (K and K) Rise
0.35
0.5
–
–
0.4
0.6
–
–
0.5
0.5
–
–
ns
ns
t
HCDDR
t
HC
0.35
–
0.4
–
0.5
–
ns
t
HD
Output Times
t
CO
t
HD
0.35
–
0.4
–
0.5
–
ns
t
CHQV
C/C Clock Rise (or K/K in Single Clock Mode)
to Data Valid
Data Output Hold after Output C/C Clock
Rise (Active to Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Clock (C and C) Rise to High-Z (Active to
High-Z)
[17,18]
Clock (C and C) Rise to Low-Z
[17,18]
–
0.45
–
0.45
–
0.50
ns
t
DOH
t
CHQX
–0.45
–
-0.45
–
-0.50
–
ns
t
CCQO
t
CQOH
t
CQD
t
CQDOH
t
CHZ
t
CHCQV
t
CHCQX
t
CQHQV
t
CQHQX
t
CHZ
–
0.45
–
0.30
–
0.45
–
0.45
–
0.35
–
0.45
–
0.50
–
0.40
–
0.50
ns
ns
ns
ns
ns
–0.45
–
–0.30
–
–0.45
–
–0.35
–
–0.50
–
–0.40
–
t
CLZ
DLL Timing
t
KC Var
t
KC lock
t
KC Reset
Shaded areas contain advance information.
Please contact your local Cypress Sales representative for availability of these parts.
Notes:
15.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
16.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250
, V
DDQ
= 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified I
/I
and load capacitance shown in (a) of AC Test Loads.
17.t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
100 mV from steady-state voltage.
18.At any given voltage and temperature t
is less than t
and t
less than t
.
19.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation
can be initiated.
t
CLZ
–0.45
–
–0.45
–
–0.50
–
ns
t
KC Var
t
KC lock
t
KC Reset
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
–
0.20
–
–
–
0.20
–
–
–
0.20
–
–
ns
1024
30
1024
30
1024
30
cycles
ns
相關(guān)PDF資料 |
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| CY7C1314BV18-200BZC | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1314BV18-250BZC | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1910BV18 | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1310BV18-167BZC | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1910BV18-167BZC | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1314BV18-167BZI | 功能描述:靜態(tài)隨機(jī)存取存儲器 512Kx36 1.8V QDR II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1314BV18-200BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 512Kx36 1.8V COM QDR II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1314BV18-200BZXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1314BV18-250BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 512Kx36 1.8V QDR II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1314BV18-250BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 512KX36 0.45NS 165FBGA - Bulk |
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