參數(shù)資料
型號(hào)： CY7C1310BV18-167BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 18-Mbit QDR-II SRAM 2-Word Burst Architecture
中文描述： 2M X 8 QDR SRAM, 0.5 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁(yè)數(shù)： 10/23頁(yè)
文件大?。?/td> 262K
代理商： CY7C1310BV18-167BZC
PRELIMINARY
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Document #: 38-05619 Rev. **
Page 10 of 23
L
H
–
L-H During the Data portion of a Write sequence
:
CY7C1310BV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will
remain unaltered,
CY7C1312BV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will
remain unaltered.
–
During the Data portion of a Write sequence
:
CY7C1310BV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1312BV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will
remain unaltered.
L-H During the Data portion of a Write sequence
:
CY7C1310BV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1312BV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will
remain unaltered.
–
No data is written into the devices during this portion of a Write operation.
L-H No data is written into the devices during this portion of a Write operation.
H
L
L-H
H
L
–
H
H
H
H
L-H
–
Write Cycle Descriptions
(CY7C1314BV18)
[2, 8]
BWS
0
BWS
1
L
BWS
2
L
BWS
3
L
K
K
-
Comments
L
L-H
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are written
into the device.
L-H During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are written
into the device.
-
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
will remain unaltered.
-
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
will remain unaltered.
-
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
will remain unaltered.
-
No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
L
L
L
L
-
L
H
H
H
L-H
L
H
H
H
-
H
L
H
H
L-H
H
L
H
H
-
H
H
L
H
L-H
H
H
L
H
-
H
H
H
L
L-H
H
H
H
L
-
H
H
H
H
H
H
H
H
L-H
-
Write Cycle Descriptions
(CY7C1910BV18)
BWS
0
L
K
K
–
Comments
L-H
During the Data portion of a Write sequence
:
CY7C1910BV18
the single byte
(D
[8:0]
) is written into the device
During the Data portion of a Write sequence
:
CY7C1910BV18
the single byte
(D
[8:0]
) is written into the device,
No data is written into the devices during this portion of a Write operation.
No data is written into the devices during this portion of a Write operation.
L
–
L-H
H
H
L-H
–
–
L-H
Write Cycle Descriptions
(CY7C1310BV18 and CY7C1312BV18) (continued)
[2, 8]
BWS
0
/
NWS
0
BWS
1
/
NWS
1
K
K
Comments
相關(guān)PDF資料
PDF描述
CY7C1910BV18-167BZC 18-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1310BV18-200BZC 18-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1910BV18-200BZC 18-Mbit QDR-II SRAM 2-Word Burst Architecture
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CY7C1910BV18-250BZC 18-Mbit QDR-II SRAM 2-Word Burst Architecture
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