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參數(shù)資料
| 型號： | CY7C1307BV25-167BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
| 中文描述： | 512K X 36 QDR SRAM, 2.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 247K |
| 代理商： | CY7C1307BV25-167BZC |
PRELIMINARY
CY7C1305BV25
CY7C1307BV25
Document #: 38-05630 Rev. **
Page 7 of 21
Truth Table
[2, 3, 4, 5, 6, 7, 8, 9]
Operation
K
RPS
H
[8]
WPS
L
[9]
DQ
DQ
DQ
DQ
Write Cycle
:
Load address on the rising edge
of K; wait one cycle; input write
data on two consecutive K and K
rising edges.
Read Cycle
:
Load address on the rising edge
of K; wait one cycle; read data on
two consecutive C and C rising
edges.
NOP
:
No operation
L-H
D(A+00)at
K(t+1)
↑
D(A+01) at
K(t+1)
↑
D(A+10) at
K(t+2)
↑
D(A+11) at
K(t+2)
↑
L-H
L
[9]
X
Q(A+00) at
C(t+1)
↑
Q(A+01) at
C(t+1)
↑
Q(A+10) at
C(t+2)
↑
Q(A+11) at
C(t+2)
↑
L-H
H
H
D = X
Q = High-Z
Previous state Previous state Previous
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
Previous
state
Standby
:
Clock stopped
Stopped
X
X
state
Write Cycle Descriptions (CY7C1305BV25)
[2, 10]
BWS
0
L
L
L
BWS
1
L
L
H
K
K
–
Comments
L-H
–
L-H
During the Data portion of a Write sequence, both bytes (D
[17:0]
) are written into the device.
During the Data portion of a Write sequence, both bytes (D
[17:0]
) are written into the device.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written into the
device. D
[17:9]
will remain unaltered.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written into the
device. D
[17:9]
will remain unaltered.
During the Data portion of a Write sequence, only the upper byte (D
[17:9]
) is written into
the device. D
[8:0]
will remain unaltered.
During the Data portion of a Write sequence, only the upper byte (D
[17:9]
) is written into
the device. D
[8:0]
will remain unaltered.
No data is written into the device during this portion of a Write operation.
No data is written into the device during this portion of a Write operation.
L-H
–
L
H
–
L-H
H
L
L-H
–
H
L
–
L-H
H
H
H
H
L-H
–
–
L-H
Notes:
2. X = Don't Care, H = Logic HIGH, L = Logic LOW,
↑
represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01, A+10 and A+11 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a don’t care for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read request.
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| CY7C1308DV25C-167BZCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx36 2.5V DDR 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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