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參數(shù)資料
| 型號： | CY7C1307BV25-167BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
| 中文描述： | 512K X 36 QDR SRAM, 2.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 247K |
| 代理商： | CY7C1307BV25-167BZC |
PRELIMINARY
CY7C1305BV25
CY7C1307BV25
Document #: 38-05630 Rev. **
Page 4 of 21
Pin Definitions
Name
I/O
Input-
Description
D
[x:0]
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations
.
CY7C1305BV25 – D
[17:0]
CY7C1307BV25 – D
[35:0]
Write Port Select, active LOW
. Sampled on the rising edge of the K clock. When
asserted active, a Write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D
[x:0]
to be ignored.
Byte Write Select 0, 1, 2, and 3–active LOW
.
Sampled on the rising edge of the K and
K clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations. Bytes not written remain unaltered.
CY7C1305BV25 - BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1307BV25 - BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27]
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a
Byte Write Select will cause the corresponding byte of data to be ignored and not written
into the device.
Address Inputs
. Sampled on the rising edge of the K clock during active Read and Write
operations. These address inputs are multiplexed for both Read and Write operations.
Internally, the device is organized as 1M x 18 (4 arrays each of 256K x 18) for
CY7C1305BV25 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1307BV25.
Therefore, only 18 address inputs for CY7C1305BV25 and 17 address inputs for
CY7C1307BV25. These inputs are ignored when the appropriate port is deselected.
Data Output signals
. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q
[x:0]
are automatically three-stated.
CY7C1305BV25 - Q
[17:0]
CY7C1307BV25 - Q
[35:0]
Read Port Select, active LOW
. Sampled on the rising edge of Positive Input Clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically three-stated following the next rising edge of the C clock. Each
read access consists of a burst of four sequential 18-bit or 36-bit transfers.
Positive Output Clock Input
. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
Negative Output Clock Input
.
C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various
devices on the board cack to the controller. See application example for further details.
Positive Input Clock Input
. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q
[x:0]
when in single clock mode. All accesses
are initiated on the rising edge of K.
Negative Input Clock Input
. K is used to capture synchronous inputs to the device and
to drive out data through Q
[x:0]
when in single clock mode.
Output Impedance Matching Input
.
This input is used to tune the device outputs to the
system data bus impedance. Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is
a resistor connected between ZQ and ground. Alternately, this pin can be connected
directly to V
DD
, which enables the minimum impedance mode. This pin cannot be
connected directly to VSS or left unconnected.
TDO pin for JTAG
TCK pin for JTAG
TDI pin for JTAG
TMS pin for JTAG
WPS
Input-
Synchronous
BWS
0
, BWS
1
,
BWS
2
, BWS
3
Input-
Synchronous
A
Input-
Synchronous
Q
[x:0]
Outputs-
Synchronous
RPS
Input-
Synchronous
C
Input-Clock
C
Input-Clock
K
Input-Clock
K
Input-Clock
ZQ
Input
TDO
TCK
TDI
TMS
Output
Input
Input
Input
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相關(guān)代理商/技術(shù)參數(shù) |
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| CY7C1308BV25-167BZC | 制造商:Cypress Semiconductor 功能描述:256KX36 2.5V DDR SRAM (4-WORD BURST) - Bulk |
| CY7C1308DV25-250BZC | 制造商:Cypress Semiconductor 功能描述:256KX36 2.5V DDR SRAM (4-WORD BURST) - Bulk |
| CY7C1308DV25C-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx36 2.5V DDR 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1308DV25C-167BZCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx36 2.5V DDR 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1308SV25C-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 CY7C1308SV25C-167BZC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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