參數(shù)資料
型號: CY7C1307BV25-167BZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
中文描述: 512K X 36 QDR SRAM, 2.5 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù): 12/21頁
文件大?。?/td> 247K
代理商: CY7C1307BV25-167BZC
PRELIMINARY
CY7C1305BV25
CY7C1307BV25
Document #: 38-05630 Rev. **
Page 12 of 21
Switching Waveforms
[23, 24, 25]
Notes:
23.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
24.Outputs are disabled (High-Z) one clock cycle after a NOP.
25.In this example, if address A2 = A1 then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results.This note applies to the whole diagram.
K
1
2
3
4
5
6
7
K
RPS
WPS
A
Q
D
C
C
A0
READ
READ
WRITE
WRITE
Q00
Q03
D10
D11
D12
D13
D30
D31
D32
D33
A1
t
KH
t
KHKH
t
KHCH
t
CO
t
DOH
t
KL
t
CYC
t
t
HC
t
SA
t
HA
t
SD
t
HD
tKHCH
Q01
Q02
Q23
Q22
Q20
Q21
NOP
NOP
Qx3
A2
t
SD
t
HD
DON’T CARE
UNDEFINED
t
CLZ
tCO
t
DOH
tCHZ
SC
t
t
HC
SC
tKH
tKHKH
tKL
tCYC
A3
相關(guān)PDF資料
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CY7C1305BV25-133BZC 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
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