參數(shù)資料
型號： CY7C1307BV25-133BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
中文描述： 512K X 36 QDR SRAM, 3 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
文件頁數(shù)： 9/21頁
文件大?。?/td> 247K
代理商： CY7C1307BV25-133BZC
PRELIMINARY
CY7C1305BV25
CY7C1307BV25
Document #: 38-05630 Rev. **
Page 9 of 21
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DD
Relative to GND........–0.5V to +3.6V
DC Applied to Outputs in High-Z State –0.5V to V
DDQ
+ 0.5V
DC Input Voltage
[11]
............................ –0.5V to V
DDQ
+ 0.5V
Electrical Characteristics
Over the Operating Range
[13]
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current................................................... > 200 mA
Operating Range
Range
Com’l
Ambient
Temperature (T
A)
0°C to +70°C
V
DD
[12]
2.5 ± 0.1V
V
DDQ
[12]
1.4V to 1.9V
DC Electrical Characteristics Over the Operating Range
Parameter
V
DD
V
DDQ
V
OH
V
OL
V
OH(LOW)
V
OL(LOW)
V
IH
V
IL
I
X
I
OZ
V
REF
I
DD
Description
Test Conditions
Min.
2.4
1.4
Typ.
2.5
1.5
Max.
2.6
1.9
Unit
V
V
V
V
V
V
V
V
μ
A
μ
A
V
mA
mA
mA
mA
mA
mA
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
[11]
Input LOW Voltage
[11, 16]
Input Load Current
Output Leakage Current
Input Reference Voltage
[17]
V
DD
Operating Supply
Note 14
Note 15
I
OH
= –0.1 mA, Nominal Impedance
I
OH
= 0.1 mA, Nominal Impedance
V
DDQ
/2 – 0.12
V
DDQ
/2
– 0.12
V
DDQ
– 0.2
V
SS
V
REF
+ 0.1
–0.3
–5
–5
0.68
V
DDQ
/2 + 0.12
V
DDQ
/2 + 0.12
V
DDQ
0.2
V
DDQ
+ 0.3
V
REF
– 0.1
5
5
0.95
TBD
TBD
TBD
TBD
TBD
TBD
GND
≤
V
I
≤
V
DDQ
GND
≤
V
I
≤
V
DDQ,
Output Disabled
Typical value = 0.75V
V
DD
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
0.75
167 MHz
133 MHz
100 MHz
167 MHz
133 MHz
100 MHz
I
SB1
Automatic
Power-Down
Current
Max. V
DD
, Both Ports
Deselected,
V
IN
≤
V
IH
or V
IN
< V
IL
f = f
MAX
= 1/t
CYC,
Inputs Static
AC Input Requirements Over the Operating Range
Test Conditions
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Parameter
V
IH
V
IL
Description
Min.
Typ.
–
–
Max.
–
Unit
V
V
V
REF
+ 0.2
–
V
REF
– 0.2
Thermal Resistance
[18]
Parameter
Θ
JA
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
165 FBGA
Package
16.7
Unit
°
C/W
Test conditions follow standard test methods and proce-
dures for measuring thermal impedance, per
EIA/JESD51.
Θ
JC
2.5
°
C/W
Notes:
11. Overshoot: V
(AC) < V
+0.85V (Pulse width less than t
/2), Undershoot: V
IL
(AC) > –1.5V (Pulse width less than t
CYC
/2).
12.Power-up: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
13.All Voltage referenced to Ground.
14.Output are impedance controlled. I
OH
= –(V
DDQ
/2)/(RQ/5) for values of 175
<= RQ <= 350
.
15.Output are impedance controlled. I
= (V
2)/(RQ/5) for values of 175
<= RQ <= 350
.
16.This spec is for all inputs except C and C Clock. For C and C Clock, V
(Max.) = V
REF
– 0.2V.
17.V
REF
(Min.) = 0.68V or 0.46V
DDQ
, whichever is larger, V
REF
(Max.) = 0.95V or 0.54V
DDQ
, whichever is smaller.
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