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參數(shù)資料
| 型號： | CY7C1307BV25-133BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
| 中文描述： | 512K X 36 QDR SRAM, 3 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165 |
| 文件頁數(shù)： | 16/21頁 |
| 文件大小： | 247K |
| 代理商： | CY7C1307BV25-133BZC |
PRELIMINARY
CY7C1305BV25
CY7C1307BV25
Document #: 38-05630 Rev. **
Page 16 of 21
TAP Controller Block Diagram
TAP Electrical Characteristics
Over the Operating Range
[11, 13, 27]
Parameter
V
OH1
V
OH2
V
OL1
V
OL2
V
IH
V
IL
I
X
Description
Test Conditions
I
OH
=
2.0 mA
I
OH
=
100
μ
A
I
OL
= 2.0 mA
I
OL
= 100
μ
A
Min.
1.7
2.1
Max.
Unit
V
V
V
V
V
V
μ
A
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input and Output Load Current
0.7
0.2
1.7
–0.3
5
V
DD
+ 0.3
0.7
5
GND
≤
V
I
≤
V
DDQ
TAP AC Switching Characteristics
Over the Operating Range
[28, 29]
Parameter
t
TCYC
t
TF
t
TH
t
TL
Set-up Times
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
t
CH
Notes:
27.These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
28.Parameters t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
29.Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns.
Description
Min.
100
Max.
Unit
ns
MHz
ns
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
TCK Clock LOW
10
40
40
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
10
10
10
ns
ns
ns
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
106
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
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