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參數(shù)資料
| 型號： | CY7C1307BV25-133BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
| 中文描述： | 512K X 36 QDR SRAM, 3 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大小： | 247K |
| 代理商： | CY7C1307BV25-133BZC |
PRELIMINARY
CY7C1305BV25
CY7C1307BV25
Document #: 38-05630 Rev. **
Page 10 of 21
Capacitance
[18]
Parameter
Description
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
DD
= 2.5V.
V
DDQ
= 1.5V
Max.
5
6
7
Unit
pF
pF
pF
C
IN
C
CLK
C
O
Input Capacitance
Clock Input Capacitance
Output Capacitance
AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range
[19]
Cypress
Parameter
t
Power[20]
Cycle Time
t
CYC
t
KH
t
KL
t
KHKH
Consortium
Parameter
Description
167 MHz
Min.
10
133 MHz
Min.
10
100 MHz
Min.
10
Unit
μ
s
Max.
Max.
Max.
V
CC
(typical) to the First Access Read or Write
t
KHKH
t
KHKL
t
KLKH
t
KHKH
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
K/K Clock Rise to K/K Clock Rise and C/C to C/C
Rise (rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to
rising edge)
6.0
2.4
2.4
2.7
7.5
3.2
3.2
3.4
10.0
3.5
3.5
4.4
ns
ns
ns
ns
3.3
4.1
5.4
t
KHCH
t
KHCH
0.0
2.0
0.0
2.5
0.0
3.0
ns
Set-up Times
t
SA
t
SC
t
SA
t
SC
Address Set-up to Clock (K and K) Rise
Control Set-up to Clock (K and K) Rise (RPS,
WPS, BWS
0
, BWS
1
)
D
[x:0]
Set-up to Clock (K and K) Rise
0.7
0.7
0.8
0.8
1.0
1.0
ns
ns
t
SD
Hold Times
t
HA
t
HC
t
SD
0.7
0.8
1.0
ns
t
HA
t
HC
Address Hold after Clock (K and K) Rise
Control Signals Hold after Clock (K and K) Rise
(RPS, WPS, BWS
0
, BWS
1
)
D
[x:0]
Hold after Clock (K and K) Rise
0.7
0.7
0.8
0.8
1.0
1.0
ns
ns
t
HD
Output Times
t
CO
t
HD
0.7
0.8
1.0
ns
t
CHQV
C/C Clock Rise (or K/K in single clock mode) to
Data Valid
[21]
2.5
3.0
3.0
ns
Note:
18.Tested initially and after any design or process change that may affect these parameters.
1.25V
0.25V
R = 50
5 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
Device
Under
Test
R
L
= 50
Z
0
= 50
V
REF
= 0.75V
V
DDQ
/2
[18]
0.75V
V
DDQ
/2
Device
Under
Test
OUTPUT
V
DDQ
/2
V
REF
V
REF
OUTPUT
ZQ
ZQ
(a)
RQ =
250
(b)
RQ=
250
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| CY7C1307BV25-167BZC | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1308BV25-167BZC | 制造商:Cypress Semiconductor 功能描述:256KX36 2.5V DDR SRAM (4-WORD BURST) - Bulk |
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| CY7C1308DV25C-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx36 2.5V DDR 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1308DV25C-167BZCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx36 2.5V DDR 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1308SV25C-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 CY7C1308SV25C-167BZC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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