參數(shù)資料
型號(hào)： CY7C1307BV25-100BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
中文描述： 512K X 36 QDR SRAM, 3 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù)： 8/21頁(yè)
文件大小： 247K
代理商： CY7C1307BV25-100BZC
PRELIMINARY
CY7C1305BV25
CY7C1307BV25
Document #: 38-05630 Rev. **
Page 8 of 21
Write Cycle Descriptions
(CY7C1307BV25)
[2, 10
]
BWS
0
L
BWS
1
L
BWS
2
L
BWS
3
L
K
K
–
Comments
L-H
During the Data portion of a Write sequence, all four bytes
(D
[35:0]
) are written into the device.
During the Data portion of a Write sequence, all four bytes
(D
[35:0]
) are written into the device.
During the Data portion of a Write sequence, only the lower
byte (D
[8:0]
) is written into the device. D
[35:9]
will remain
unaltered.
During the Data portion of a Write sequence, only the lower
byte (D
[8:0]
) is written into the device. D
[35:9]
will remain
unaltered.
During the Data portion of a Write sequence, only the byte
(D
[17:9]
) is written into the device. D
[8:0]
and D
[35:18]
will
remain unaltered.
During the Data portion of a Write sequence, only the byte
(D
[17:9]
) is written into the device. D
[8:0]
and D
[35:18]
will
remain unaltered.
During the Data portion of a Write sequence, only the byte
(D
[26:18]
) is written into the device. D
[17:0]
and D
[35:27]
will
remain unaltered.
During the Data portion of a Write sequence, only the byte
(D
[26:18]
) is written into the device. D
[17:0]
and D
[35:27]
will
remain unaltered.
During the Data portion of a Write sequence, only the byte
(D
[35:27]
) is written into the device. D
[26:0]
will remain
unaltered.
During the Data portion of a Write sequence, only the byte
(D
[35:27]
) is written into the device. D
[26:0]
will remain
unaltered.
No data is written into the device during this portion of a Write
operation.
No data is written into the device during this portion of a write
operation.
L
L
L
L
–
L-H
L
H
H
H
L-H
–
L
H
H
H
–
L-H
H
L
H
H
L-H
–
H
L
H
H
–
L-H
H
H
L
H
L-H
–
H
H
L
H
–
L-H
H
H
H
L
L-H
H
H
H
L
–
L-H
H
H
H
H
L-H
–
H
H
H
H
–
L-H
Note:
10.Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS
and BWS
in the case of CY7C1305BV25 and BWS
2
and BWS
3
in
the case of CY7C1307BV25 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.
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參數(shù)描述
CY7C1308BV25-167BZC 制造商:Cypress Semiconductor 功能描述:256KX36 2.5V DDR SRAM (4-WORD BURST) - Bulk
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CY7C1308DV25C-167BZCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 2.5V DDR 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1308SV25C-167BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 CY7C1308SV25C-167BZC RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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