參數(shù)資料
型號: CY7C1305BV25-133BZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
中文描述: 1M X 18 QDR SRAM, 3 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
文件頁數(shù): 8/21頁
文件大?。?/td> 247K
代理商: CY7C1305BV25-133BZC
PRELIMINARY
CY7C1305BV25
CY7C1307BV25
Document #: 38-05630 Rev. **
Page 8 of 21
Write Cycle Descriptions
(CY7C1307BV25)
[2, 10
]
BWS
0
L
BWS
1
L
BWS
2
L
BWS
3
L
K
K
Comments
L-H
During the Data portion of a Write sequence, all four bytes
(D
[35:0]
) are written into the device.
During the Data portion of a Write sequence, all four bytes
(D
[35:0]
) are written into the device.
During the Data portion of a Write sequence, only the lower
byte (D
[8:0]
) is written into the device. D
[35:9]
will remain
unaltered.
During the Data portion of a Write sequence, only the lower
byte (D
[8:0]
) is written into the device. D
[35:9]
will remain
unaltered.
During the Data portion of a Write sequence, only the byte
(D
[17:9]
) is written into the device. D
[8:0]
and D
[35:18]
will
remain unaltered.
During the Data portion of a Write sequence, only the byte
(D
[17:9]
) is written into the device. D
[8:0]
and D
[35:18]
will
remain unaltered.
During the Data portion of a Write sequence, only the byte
(D
[26:18]
) is written into the device. D
[17:0]
and D
[35:27]
will
remain unaltered.
During the Data portion of a Write sequence, only the byte
(D
[26:18]
) is written into the device. D
[17:0]
and D
[35:27]
will
remain unaltered.
During the Data portion of a Write sequence, only the byte
(D
[35:27]
) is written into the device. D
[26:0]
will remain
unaltered.
During the Data portion of a Write sequence, only the byte
(D
[35:27]
) is written into the device. D
[26:0]
will remain
unaltered.
No data is written into the device during this portion of a Write
operation.
No data is written into the device during this portion of a write
operation.
L
L
L
L
L-H
L
H
H
H
L-H
L
H
H
H
L-H
H
L
H
H
L-H
H
L
H
H
L-H
H
H
L
H
L-H
H
H
L
H
L-H
H
H
H
L
L-H
H
H
H
L
L-H
H
H
H
H
L-H
H
H
H
H
L-H
Note:
10.Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS
and BWS
in the case of CY7C1305BV25 and BWS
2
and BWS
3
in
the case of CY7C1307BV25 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.
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