參數(shù)資料
型號(hào): CY7C1305BV25-133BZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
中文描述: 1M X 18 QDR SRAM, 3 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù): 11/21頁(yè)
文件大小: 247K
代理商: CY7C1305BV25-133BZC
PRELIMINARY
CY7C1305BV25
CY7C1307BV25
Document #: 38-05630 Rev. **
Page 11 of 21
t
DOH
t
CHQX
Data Output Hold after Output C/C Clock Rise
(Active to Active)
Clock (C and C) rise to High-Z (Active to
High-Z)
[21, 22]
Clock (C and C) rise to Low-Z
[21, 22]
1.2
1.2
1.2
ns
t
CHZ
t
CHZ
2.5
3.0
3.0
ns
t
CLZ
Notes:
19.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,V
= 0.75V, RQ = 250
, V
DDQ
= 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified I
/I
OH
and load capacitance shown in (a) of AC Test Loads.
20.This part has a voltage regulator that steps down the voltage internally; t
Power
is the time power needs to be supplied above V
DD
minimum initially before a Read
or Write operation can be initiated.
21.t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
22.At any given voltage and temperature t
CHZ
is less than t
CLZ
and, t
CHZ
less than t
CO
.
t
CLZ
1.2
1.2
1.2
ns
Switching Characteristics
Over the Operating Range
[19]
(continued)
Cypress
Parameter
Consortium
Parameter
Description
167 MHz
Min.
133 MHz
Min.
100 MHz
Min.
Unit
Max.
Max.
Max.
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