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參數(shù)資料
| 型號： | CY7C1304V25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mb Pipelined SRAM with QDR Architecture(帶QDR結(jié)構(gòu)的9-M位流水線式 SRAM) |
| 中文描述： | 9 - MB的流水線架構(gòu)的SRAM與國防評估報告（帶國防評估報告結(jié)構(gòu)的9米位流水線式的SRAM） |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 216K |
| 代理商： | CY7C1304V25 |
CY7C1304V25
Advanced Information
4
Introduction
Functional Overview
The CY7C1304V25 is a synchronous pipelined Burst SRAM
equipped with both a Read Port and a Write Port. The Read
port is dedicated to Read operations and the Write Port is ded-
icated to Write operations. Data flows into the SRAM through
the Write port and out through the Read Port. The
CY7C1304V25 multiplexes the address inputs in order to min-
imize the number of address pins required. By having separate
Read and Write ports, the CY7C1304V25 completely elimi-
nates the need to
“
turn-around
”
the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of 4 18-bit data transfers in two clock
cycles.
Accesses for both ports are initiated on the Positive Input
Clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the output clocks (C and C or K and K when
in single clock mode).
All synchronous data inputs (D
[17:0]
) inputs pass through input
registers controlled by the input clocks (K and K). All synchro-
nous data outputs (Q
[17:0]
) outputs pass through output regis-
ters controlled by the rising edge of the output clocks (C and
C or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS
0
, BWS
1
) inputs
pass through input registers controlled by the rising edge of
the input clocks (K and K, C and C).
Read Operations
The CY7C1304V25 is organized internally as a 128Kx72
SRAM. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS
active at the rising edge of the Positive Input Clock (K).
The address presented to Address inputs are stored in the
Read address register. Following the next K clock rise the cor-
responding lowest order 18-bit word of data is driven onto the
Q
[17:0]
using C as the output timing reference. On the subse-
quent rising edge of C the next 18-bit data word is driven onto
the Q
[17:0]
. This process continues until all four 18-bit data
words have been driven out onto Q
[17:0]
. The requested data
will be valid 2.5ns from the rising edge of the output clock (C
or C, 167MHz device). In order to maintain the internal logic,
each read access must be allowed to complete. Each Read
access consists of 4 18-bit data words and takes 2 clock cycles
to complete. Therefore, Read accesses to the device can not
be initiated on two consecutive K clock rises. The internal logic
of the device will ignore the second Read request. Read ac-
cesses can be initiated on every other K clock rise. Doing so
will pipeline the data flow such that data is transferred out of
the device on every rising edge of the output clocks (C and C
or K and K when in single clock mode).
When the read port is deselected, the CY7C1304V25 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically three-state the outputs following the
next rising edge of the Negative Output Clock (C). This will
allow for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the following K
clock rise the data presented to D
[17:0]
is latched and stored
into the lower 18-bit Write Data register provided BWS
[1:0]
are
both asserted active. On the subsequent rising edge of the
Negative Input Clock (K) the information presented to D
[17:0]
is
also stored into the Write Data Register provided BWS
[1:0]
are
both asserted active. This process continues for one more cy-
cle until 4 18-bit words (a total of 72 bits) of data are stored in
the SRAM. The 72 bits of data are then written into the memory
array at the specified location. Therefore, Write accesses to
the device can not be initiated on two consecutive K clock ris-
es. The internal logic of the device will ignore the second Write
request. Write accesses can be initiated on every other rising
edge of the Positive Input Clock (K). Doing so will pipeline the
data flow such that 18-bits of data can be transferred into the
device on every rising edge of the input clocks (K and K).
When deselected, the write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1304V25. A
write operation is initiated as described in the Write Operation
section above. The bytes that are written are determined by
BWS
0
and BWS
1
which are sampled with each set of 18-bit
data word. Asserting the appropriate Byte Write Select input
during the data portion of a write will allow the data being pre-
sented to be latched and written into the device. De-asserting
the Byte Write Select input during the data portion of a write
will allow the data stored in the device for that byte to remain
unaltered. This feature can be used to simplify READ/MODI-
FY/WRITE operations to a Byte Write operation.
Single Clock Mode
The CY7C1304V25 can be used with a single clock that con-
trols both the input and output registers. In this mode the de-
vice will recognize only a single pair of input clocks (K and K)
that control both the input and output registers. This operation
is identical to the operation if the device had zero skew be-
tween the K/K and C/C clocks. All timing parameters remain
the same in this mode. To use this mode of operation, the user
V
REF
Input-
Reference
Power Supply
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
Outputs as well as A/C measurement points.
Power supply inputs to the core of the device. Should be connected to 2.5V power
supply.
Ground for the device. Should be connected to ground of the system.
Power supply inputs for the outputs of the device. Should be connected to 1.5V power
supply.
No connect
V
DD
V
SS
V
DDQ
Ground
Power Supply
NC
NC
Pin Definitions
(continued)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1304V25-200BZC | 制造商:Cypress Semiconductor 功能描述:9MB PIPELINE QDR SRAM 2.5V CORE, FBGA - Trays |
| CY7C1305 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C13055DC | 制造商:CYPRESS 功能描述:* |
| CY7C130-55PC | 功能描述:靜態(tài)隨機存取存儲器 1K x 8 Dual-Port 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1305BV25-167BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mx18 2.5V QDR 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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