參數(shù)資料
型號(hào): CY7C1304V25
廠商: Cypress Semiconductor Corp.
英文描述: 9-Mb Pipelined SRAM with QDR Architecture(帶QDR結(jié)構(gòu)的9-M位流水線式 SRAM)
中文描述: 9 - MB的流水線架構(gòu)的SRAM與國(guó)防評(píng)估報(bào)告(帶國(guó)防評(píng)估報(bào)告結(jié)構(gòu)的9米位流水線式的SRAM)
文件頁(yè)數(shù): 12/23頁(yè)
文件大?。?/td> 216K
代理商: CY7C1304V25
CY7C1304V25
Advanced Information
12
TAP Controller Block Diagram
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
68
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
TAP Electrical Characteristics
Over the Operating Range
[9, 10, 11]
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
OH1
Output HIGH Voltage
I
OH
=
2.0mA
I
OH
=
100
μ
A
1.7
V
V
OH2
Output HIGH Voltage
2.1
V
V
OL1
Output LOW Voltage
I
OL
= 2.0mA
I
OL
= 100
μ
A
0.7
V
V
OL2
Output LOW Voltage
0.2
V
V
IH
Input HIGH Voltage
1.7
V
DD
+0.3
V
V
IL
Input LOW Voltage
0.3
0.7
V
I
X
Input and OutputLoad Current
GND
V
I
V
DDQ
5
5
μ
A
9.
10. Overshoot: V
(AC)<V
+1.5V for t<t
/2, Undershoot V
(AC)<0.5V for t<t
/2, Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V for t<200ms.
11. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
All Voltage referenced to Ground.
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