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參數(shù)資料
| 型號： | CY7C1303BV25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture(18Mbit，Burst of 2，QDR結(jié)構(gòu)，流水線SRAM) |
| 中文描述： | 18兆位的2四年防務(wù)審查架構(gòu)（18Mbit，2突發(fā)流水線SRAM的突發(fā)，國防評估報告結(jié)構(gòu)，流水線的SRAM） |
| 文件頁數(shù)： | 6/19頁 |
| 文件大小： | 821K |
| 代理商： | CY7C1303BV25 |
CY7C1306BV25
CY7C1303BV25
Document #: 38-05627 Rev. *A
Page 6 of 19
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-up.This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1303BV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor-
mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
Depth Expansion
The CY7C1303BV25 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
SS
to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175
and 350
,
with
V
DDQ
=1.5V. The output impedance is adjusted every 1024
cycles to account for drifts in supply voltage and temperature.
Truth Table
[2, 3, 4, 5, 6, 7]
Application Example
[1]
Operation
K
RPS
X
WPS
L
DQ
DQ
Write Cycle:
Load address on the rising edge of K clock; input write
data on K and K rising edges.
Read Cycle:
Load address on the rising edge of K clock; wait one
cycle; read data on 2 consecutive C and C rising edges.
NOP: No Operation
L-H
D(A+0) at
K(t)
↑
D(A+1) at
K(t)
↑
L-H
L
X
Q(A+0) at
C(t+1)
↑
Q(A+1) at
C(t+1)
↑
L-H
H
H
D = X
Q = High-Z
Previous
State
D = X
Q = High-Z
Previous
State
Standby: Clock Stopped
Stopped
X
X
Notes:
1. The above application shows 4 QDR-I being used.
2. X = Don't Care, H = Logic HIGH, L = Logic LOW,
↑
represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1303BV25-167BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mx18 2.5V QDR 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1303BV25-167BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 1MX18 2.5NS 165FBGA - Bulk |
| CY7C1303TV25-167BZC | 功能描述:靜態(tài)隨機存取存儲器 NV靜態(tài)隨機存取存儲器 167 MHz 2.5V RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1303V25-133BZC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 2.5V 18MBIT 1MX18 3NS 165FBGA - Trays |
| cy7c1303v25-167bzc | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 2.5V 18MBIT 1MX18 2.5NS 165FBGA - Trays |
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