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參數(shù)資料
| 型號(hào)： | CY7C1303BV25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture(18Mbit，Burst of 2，QDR結(jié)構(gòu)，流水線SRAM) |
| 中文描述： | 18兆位的2四年防務(wù)審查架構(gòu)（18Mbit，2突發(fā)流水線SRAM的突發(fā)，國(guó)防評(píng)估報(bào)告結(jié)構(gòu)，流水線的SRAM） |
| 文件頁(yè)數(shù)： | 16/19頁(yè) |
| 文件大?。?/td> | 821K |
| 代理商： | CY7C1303BV25 |
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CY7C1306BV25
CY7C1303BV25
Document #: 38-05627 Rev. *A
Page 16 of 19
Capacitance
[23]
Parameter
C
IN
C
CLK
C
O
Description
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
DD
= 2.5V.
V
DDQ
= 1.5V
Max.
5
6
7
Unit
pF
pF
pF
Input Capacitance
Clock Input Capacitance
Output Capacitance
AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range
[21]
Cypress
Parameter
t
Power[22]
Cycle Time
t
CYC
t
KH
t
KL
t
KHKH
Consortium
Parameter
Description
167 MHz
Min.
10
Unit
μ
s
Max.
V
CC
(typical) to the First Access Read or Write
t
KHKH
t
KHKL
t
KLKH
t
KHKH
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise
(rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
6.0
2.4
2.4
2.7
ns
ns
ns
ns
3.3
t
KHCH
Set-up Times
t
SA
t
SC
t
SD
Hold Times
t
HA
t
HC
t
HD
Output Times
t
CO
t
DOH
t
CHZ
t
CLZ
Notes:
21.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250
, V
DDQ
= 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified I
/I
OH
and load capacitance shown in (a) of AC test loads.
22.This part has a voltage regulator that steps down the voltage internally; t
Power
is the time power needs to be supplied above V
DD
minimum initially before a read
or write operation can be initiated.
23.At any given voltage and temperature t
CHZ
is less than t
CLZ
and, t
CHZ
less than t
CO
.
t
KHCH
0.0
2.0
ns
t
SA
t
SC
t
SD
Address Set-up to Clock (K and K) Rise
Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS
0
, BWS
1
)
D
[x:0]
Set-up to Clock (K and K) Rise
0.7
0.7
0.7
ns
ns
ns
t
HA
t
HC
t
HD
Address Hold after Clock (K and K) Rise
Control Signals Hold after Clock (K and K) Rise (RPS, WPS, BWS
0
, BWS
1
)
D
[x:0]
Hold after Clock (K and K) Rise
0.7
0.7
0.7
ns
ns
ns
t
CHQV
t
CHQX
t
CHZ
t
CLZ
C/C Clock Rise (or K/K in single clock mode) to Data Valid
Data Output Hold after Output C/C Clock Rise (Active to Active)
Clock (C and C) rise to High-Z (Active to High-Z)
[23, 24]
Clock (C and C) rise to Low-Z
[23, 24]
2.5
ns
ns
ns
ns
1.2
2.5
1.2
1.25V
0.25V
R = 50
5 pF
ALL INPUT PULSES
Device
Under
Test
R
L
= 50
Z
0
= 50
V
REF
= 0.75V
V
REF
= 0.75V
[21]
0.75V
0.75V
Device
Under
Test
OUTPUT
0.75V
V
REF
V
REF
OUTPUT
ZQ
ZQ
(a)
Slew Rate = 2 V/ns
RQ =
250
(b)
RQ =
250
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1303BV25-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 2.5V QDR 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1303BV25-167BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 1MX18 2.5NS 165FBGA - Bulk |
| CY7C1303TV25-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 NV靜態(tài)隨機(jī)存取存儲(chǔ)器 167 MHz 2.5V RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1303V25-133BZC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 2.5V 18MBIT 1MX18 3NS 165FBGA - Trays |
| cy7c1303v25-167bzc | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 2.5V 18MBIT 1MX18 2.5NS 165FBGA - Trays |
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