參數(shù)資料
型號(hào)： CY7C1250V18-300BZI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
中文描述： 1M X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁(yè)數(shù)： 19/27頁(yè)
文件大小： 1037K
代理商： CY7C1250V18-300BZI
CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Document Number: 001-06348 Rev. *C
Page 19 of 27
Power Up Sequence in DDR-II+ SRAM
DDR-II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL is locked after
2048 cycles of stable clock.
Power Up Sequence
Apply power with DOFF tied HIGH (all other inputs can be
HIGH or LOW)
— Apply V
DD
before V
DDQ
— Apply V
DDQ
before V
REF
or at the same time as V
REF
Provide stable power and clock (K, K) for 2048 cycles to
lock the DLL
DLL Constraints
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
KC Var
.
The DLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the DLL is enabled, then
the DLL may lock onto an incorrect frequency, causing
unstable SRAM behavior. To avoid this, provide 2048 cycles
stable clock to relock to the desired clock frequency.
Power Up Waveforms
Figure 3. Power Up Waveforms
K
K
Fix HIGH (tie to VDDQ)
VDD/VDDQ
DOFF
Clock Start (Clock Starts after VDD/VDDQ is Stable)
Unstable Clock
> 2048 Stable Clock
Start Normal
Operation
~
~
VDD/VDDQ Stable (< + 0.1V DC per 50 ns)
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1250V18-300BZXC 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1304V25 9-Mb Pipelined SRAM with QDR Architecture(帶QDR結(jié)構(gòu)的9-M位流水線式 SRAM)
CY7C1305BV25-100BZC 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1307BV25 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1307BV25-100BZC 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1250V18-333BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36M Q2+ B2 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1250V18-333BZI 制造商:Cypress Semiconductor 功能描述:
CY7C1250V18-333BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36-Mbit DDR-II+ 靜態(tài)隨機(jī)存取存儲(chǔ)器 1.8volts RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1250XC 制造商:Cypress Semiconductor 功能描述:
CY7C1262XV18-366BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB (2Mx18) 1.8v 366MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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