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參數(shù)資料
| 型號(hào)： | CY62167DV18L-55 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16M (1024K x 16) Static RAM |
| 中文描述： | 1,600（1024K × 16）靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 161K |
| 代理商： | CY62167DV18L-55 |
PRELIMINARY
CY62167DV18
MoBL2
Document #: 38-05326 Rev. *A
Page 5 of 11
Data Retention Waveform
[7]
Notes:
6.
7.
Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
μ
s or stable at V
CC(min.)
> 100
μ
s.
7. BHE
.
BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Switching Characteristics
(over the operating range)
[8]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[10]
t
HZBE
Write Cycle
[12]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Description
CY62167DV18-55
Min.
CY62167DV18-70
Min.
Unit
Max.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW or CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[9]
OE HIGH to High Z
[9, 11]
CE
1
LOW or CE
2
HIGH to Low Z
[9]
CE
1
HIGH or CE
2
LOW to High Z
[9, 11]
CE
1
LOW or CE
2
HIGH to Power-up
CE
1
HIGH or CE
2
LOW to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[9]
BLE/BHE HIGH to High-Z
[9, 11]
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
70
10
10
55
25
70
35
5
5
20
25
10
10
20
25
0
0
55
55
70
70
5
5
20
25
Write Cycle Time
CE
1
LOW or CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[9, 11]
WE HIGH to Low Z
[9]
55
40
40
0
0
40
45
25
0
70
60
60
0
0
45
60
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
10
10
V
C C (min.)
t
R
V
C C (min.)
t
C DR
V
DR
> 1.0V
DATA RETENTION MODE
C E
or
BHE.BLE
V
C C
C E
2
or
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62167DV18L-70 | FR Series Rocker, Non-lighted rectangle housing, DPDT, 3 position, Quick-connect, Snap-in panel |
| CY62167DV18LL-55 | Force Sensors; Series FSS; Non-compensated; Force Range: 0 to 1500 g |
| CY62167DV18LL-70 | 4NC Direct Opening |
| CY62167DV20L | 16-Mb (1024K x 16) Static RAM |
| CY62167DV20L-55BVI | 16-Mb (1024K x 16) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62167DV18LL-55BVI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62167DV18LL-55BVXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 SLO 1.8V SUPER LO PWR 1MEGX16 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62167DV18LL-55BVXIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 SLO 1.8V SUPER LO PWR 1MEGX16 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62167DV18LL-70BVI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 1.8V 16M-Bit 1M x 16 70ns 48-Pin VFBGA 制造商:Rochester Electronics LLC 功能描述:16M (1M X 16)- 1.8V SLOW ASYNCH SRAM - Bulk |
| CY62167DV20L-70BVI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 16M-Bit 1M x 16 70ns 48-Pin VFBGA |
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