參數(shù)資料
型號(hào): CY62167DV18
廠商: Cypress Semiconductor Corp.
英文描述: 16M (1024K x 16) Static RAM
中文描述: 1,600(1024K × 16)靜態(tài)RAM
文件頁數(shù): 6/11頁
文件大?。?/td> 161K
代理商: CY62167DV18
PRELIMINARY
CY62167DV18
MoBL2
Document #: 38-05326 Rev. *A
Page 6 of 11
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[13, 14]
Notes:
8.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of V
CC(typ.)/2
, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
10.
If both byte enables are toggled together, this value is 10 ns.
11.
t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
12.
The internal Write time of the memory is defined by the overlap of WE
, CE
1
= V
IL
, BHE and/or BLE = V
IL
.
13.
Device is continuously selected. OE
, CE
1
= V
IL
, BHE and/or BLE = V
IL
, CE
2<Def>
14.
WE
is HIGH for Read cycle.
9.
Read Cycle No. 2 (OE Controlled)
[14, 15]
ADDRESS
ATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
50%
50%
DATA VALID
t
t
t
t
t
t
HIGH IMPEDANC E
t
t
HIGH
OE
C E
1
I
C C
I
SB
IMPEDANC E
ADDRESS
C E2
VC C
SUPPLY
C URRENT
t
BHE
/
BLE
t
t
DATA OUT
t
RC
AC E
PD
HZC E
HZBE
HZOE
LZBE
DOE
LZOE
LZC E
DBE
PU
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