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參數(shù)資料
| 型號(hào)： | CY62158EV30 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Mbit (1024K x 8) Static RAM |
| 中文描述： | 8兆位（1024K × 8）靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大?。?/td> | 921K |
| 代理商： | CY62158EV30 |
CY62158EV30 MoBL
Document #: 38-05578 Rev. *D
Page 3 of 11
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential–0.3V to V
CC(max)
+ 0.3V
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
.........................–0.3V to V
CC(max)
+ 0.3V
DC Input Voltage
[5, 6]
.....................–0.3V to V
CC(max)
+ 0.3V
Electrical Characteristics
(Over the Operating Range)
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Latch up Current......................................................>200 mA
Operating Range
Product
Range
Ambient
Temperature
(T
A
)
–40°C to +85°C 2.2V – 3.6V
V
CC
[7]
CY62158EV30LL Industrial
Parameter
Description
Test Conditions
45 ns
Typ
[4]
Unit
Min
Max
V
OH
Output HIGH Voltage
I
OH
= –0.1 mA
I
OH
= –1.0 mA, V
CC
> 2.70V
I
OL
= 0.1 mA
I
OL
= 2.1 mA, V
CC
> 2.70V
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
2.0
V
2.4
V
V
OL
Output LOW Voltage
0.4
V
0.4
V
V
IH
Input HIGH Voltage
1.8
V
CC
+ 0.3V
V
CC
+ 0.3V
0.6
V
2.2
V
V
IIL
Input LOW Voltage
–0.3
V
–0.3
0.8
V
μ
A
μ
A
I
IX
I
OZ
I
CC
Input Leakage Current
–1
+1
Output Leakage Current
–1
+1
V
CC
Operating Supply Current f = f
max
= 1/t
RC
V
CC
= V
CCmax
I
OUT
= 0 mA
CMOS levels
18
25
mA
f = 1 MHz
1.8
3
mA
I
SB1
Automatic CE
Power down Current —
CMOS Inputs
CE
1
> V
CC
– 0.2V, CE
2
< 0.2V
V
IN
> V
CC
– 0.2V, V
IN
< 0.2V)
f = f
max
(Address and Data Only),
f = 0 (OE and WE), V
CC
= 3.60V
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 3.60V
2
8
μ
A
I
SB2[8]
Automatic CE
Power down Current —
CMOS Inputs
2
8
μ
A
Capacitance
[9]
Parameter
Description
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
C
IN
C
OUT
Input Capacitance
Output Capacitance
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
= V
+ 0.75V for pulse duration less than 20 ns.
7. Full device AC operation assumes a 100
μ
s ramp time from 0 to V
(min) and 200
μ
s wait time after V
stabilization.
8. Only chip enables (CE
and CE
) must be at CMOS level to meet the I
/ I
spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
[+] Feedback
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