參數(shù)資料
型號(hào)： CY62158CV33LL-70BAI
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 1024K x 8 MoBL Static RAM
中文描述： 1M X 8 STANDARD SRAM, 70 ns, PBGA48
封裝： 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
文件頁(yè)數(shù)： 6/12頁(yè)
文件大?。?/td> 256K
代理商： CY62158CV33LL-70BAI
CY62158CV25/30/33
MoBL
Document #: 38-05019 Rev. *C
Page 6 of 12
Switching Characteristics
Over the Operating Range
[7]
Parameter
Description
55 ns
70 ns
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[10]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
7.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of
the specified I
/I
and 30-pF load capacitance.
8.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
HZWE
is less than t
LZWE
for any given device.
9.
t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
10. The internal write time of the memory is defined by the overlap of WE, CE
= V
, and CE
= V
. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[8]
OE HIGH to High Z
[8, 9]
CE
1
LOW and CE
2
HIGH to Low Z
[8]
CE
1
HIGH or CE
2
LOW to High Z
[8, 9]
CE
1
LOW and CE
2
HIGH to Power-Up
CE
1
HIGH or CE
2
LOW to Power-Down
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
70
10
10
55
25
70
35
5
5
20
25
10
10
20
25
0
0
55
70
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[8, 9]
WE HIGH to Low Z
[8]
55
45
45
0
0
45
25
0
70
60
60
0
0
50
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
5
5
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