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參數(shù)資料
| 型號： | CY3683 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | MoBL-USB⑩ TX2 USB 2.0 UTMI Transceiver |
| 中文描述： | 的MoBL - USB TX2的⑩個USB 2.0收發(fā)器采用UTMI |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 490K |
| 代理商： | CY3683 |
CY7C68000A
Document #: 38-08052 Rev. *F
Page 7 of 14
56
A7
ValidH
I/O
ValidH
This signal indicates that the high-order eight bits of a 16-bit data
word presented on the
Data
bus are valid. When
DataBus16_8
= 1 and
TXValid
= 0,
ValidH
is an output, indicating that the high-order receive
data byte on the
Data
bus is valid. When
DataBus16_8
= 1 and
TXValid
= 1,
ValidH
is an input and indicates that the high-order transmit data byte,
presented on the
Data
bus by the transceiver, is valid. When
DataBus16_8
=
0, ValidH
is undefined. The status of the receive low-
order data byte is determined by
RXValid
and are present on D0–D7.
51
A2
DataBus16_8
Input
Data Bus 16_8
This signal selects between 8- and 16-bit data transfers.
1–16-bit data path operation enabled. CLK = 30 MHz.
0–8-bit data path operation enabled. When Uni_Bidi = 0, D[8:15] are un-
defined. When Uni_Bidi =1, D[0:7] are valid on TxValid and D[8:15] are
valid on RxValid. CLK = 60 MHz
Note:
DataBus16_8
is static after Power-on Reset (POR) and is only
sampled at the end of Reset.
Crystal Input
Connect this signal to a 24 MHz parallel-resonant, funda-
mental mode crystal and 20 pF capacitor to GND.
It is also correct to drive XTALIN with an external 24 MHz square wave
derived from another clock source.
Crystal Output
Connect this signal to a 24 MHz parallel-resonant, funda-
mental mode crystal and 30 pF (nominal) capacitor to GND. If an external
clock is used to drive XTALIN, leave this pin open.
Driving this pin HIGH enables the unidirectional mode when the 8-
bit interface is selected
. Uni_Bidi is static after power-on reset (POR).
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
6
H3
XTALIN
Input
N/A
5
H2
XTALOUT
Output
N/A
52
A3
Uni_Bidi
Input
55
17
28
32
45
C6
C7
D7
E7
E8
V
CC
V
CC
V
CC
V
CC
V
CC
Power
Power
Power
Power
Power
N/A
N/A
N/A
N/A
53
16
20
30
42
C4
C5
C3
D1
D2
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
N/A
N/A
N/A
N/A
N/A
Ground.
Ground.
Ground.
Ground.
Ground.
47
40
35
25
G6
F7
F2
C8
Reserved
Reserved
Reserved
Reserved
INPUT
INPUT
INPUT
INPUT
Connect pin to Ground.
Connect pin to Ground.
Connect pin to Ground.
Connect pin to Ground.
Table 1. Pin Descriptions
[1]
(continued)
QFN
VFBGA
Name
Type
Default
Description
[+] Feedback
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