參數(shù)資料
型號： CY3683
廠商： Cypress Semiconductor Corp.
英文描述： MoBL-USB⑩ TX2 USB 2.0 UTMI Transceiver
中文描述： 的MoBL - USB TX2的⑩個USB 2.0收發(fā)器采用UTMI
文件頁數(shù)： 5/14頁
文件大?。?/td> 490K
代理商： CY3683
CY7C68000A
Document #: 38-08052 Rev. *F
Page 5 of 14
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50
G8
G7
G5
G3
G2
F8
F6
F5
F4
F3
F1
G4
E1
D8
G1
E2
A1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Bidirectional Data Bus
This bidirectional bus is used as the entire data
bus in the 8-bit bidirectional mode or the least significant eight bits in the
16-bit mode. Under the 8-bit unidirectional mode, these bits are used as
inputs for data, selected by the RxValid signal.
Bidirectional Data Bus
This bidirectional bus is used as the upper eight
bits of the data bus when in the 16-bit mode, and not used when in the 8-
bit bidirectional mode. Under the 8-bit unidirectional mode these bits are
used as outputs for data, selected by the TxValid signal.
Output
Clock
This output is used for clocking the receive and transmit parallel
data on the D[15:0] bus.
Active HIGH Reset
Resets the entire chip. This pin can be tied to V
CC
through a 0.1-
μ
F capacitor and to GND through a 100 K resistor for a
10-ms RC time constant.
Transceiver Select
This signal selects between the Full-Speed (FS) and
the High-Speed (HS) transceivers:
0: HS transceiver enabled
1: FS transceiver enabled
Termination Select
This signal selects between the between the Full
Speed (FS) and the High Speed (HS) terminations:
0: HS termination
1: FS termination
Suspend
Places the CY7C68000A in a mode that draws minimal power
from supplies. Shuts down all blocks not necessary for Suspend/Resume
operations. While suspended,
TermSelect
must always be in FS mode
to ensure that the 1.5 Kohm pull up on DPLUS remains powered.
0: CY7C68000A circuitry drawing suspend current
1: CY7C68000A circuitry drawing normal current
Tri-state Mode Enable
Places the CY7C68000A into Tri-state mode
which tri-states all outputs and IO’s. Tri-state Mode can only be enabled
while suspended.
0: Disables Tri-state Mode
1: Enables Tri-state Mode
Line State
These signals reflect the current state of the single-ended
receivers. They are combinatorial until a “usable” CLK is available then
they are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
0 0 0: SE0
0 1 1: ‘J’ State
1 0 2: ‘K’ State
1 1 3: SE1
3
B2
Reset
Input
N/A
12
B3
XcvrSelect
Input
N/A
13
B4
TermSelect
Input
N/A
2
B1
Suspend
Input
N/A
24
B8
Tri_state
Input
19
C2
LineState1
Output
Table 1. Pin Descriptions
[1]
(continued)
QFN
VFBGA
Name
Type
Default
Description
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY3684 功能描述:開發(fā)板和工具包 - 其他處理器 FX2LP DVK RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
CY3684-000 制造商:TE Connectivity 功能描述:82A1121-22-9/96-9CS3022 - Bulk
CY3685 功能描述:開發(fā)板和工具包 - 其他處理器 EZ-USB NX2LP Dvel Kit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
CY3686 功能描述:開發(fā)板和工具包 - 其他處理器 NX2LP Devel Kit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
CY3687 功能描述:開發(fā)板和工具包 - 其他處理器 MoBL USB FX2LP18 DVel Kit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
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