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參數(shù)資料
| 型號： | CY2DP814SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 1:4 Clock Fanout Buffer |
| 中文描述： | LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 120K |
| 代理商： | CY2DP814SC |
ComLink
Series
CY2DP814
Document #: 38-07060 Rev. *B
Page 5 of 9
Notes:
3.
4.
5.
6.
7.
RL = 50 ohm
±
1%; Zline = 50 ohm 6
=
ó
.
CL includes instrumentation and fixture capacitance within 6 mm of the UT.
TPA and B are used for prop delay and rise/fall measurements. T
PC
is used for V
OC
measurements only and otherwise connected to V
DD
–
2.
When measuring Tr/Tf, tpd, V
point T
is held at V
–
2.0V.
LVCMOS/LVTTL single-ended input value. Ground either input: when on the B side, non-inversion takes place. If A side is grounded, the signal becomes the
complement of the input on B side. See
Table 3
.
Table 10. High-frequency Parametrics
Parameter
Description
Maximum Frequency
V
DD
= 3.3V
Conditions
Min.
Typ.
Max.
Unit
Fmax
50% Duty Cycle tW(50
–
50)
Standard Load Circuit
20% Duty Cycle tW(20
–
80)
LVPECL Input
Vin = V
IH
(Max.)/V
IL
(Min.)
Vout = V
OH
(Min.)/V
OL
(Max.) (Limit)
LVPECL Input
Vin = V
IH
(Max.)/V
IL
(Min.) F = 100 MHz
Vout = V
OH
(Min.)/V
OL
(Max.).(Limit)
450
MHz
Fmax(20)
Maximum Frequency
V
DD
= 3.3V
175
MHz
TW
Minimum Pulse
V
DD
= 3.3V
900
pS
Q
Q
VDD
VDD - 2V
Device concept
User Defined
VTT & RTT
Figure 1. Differential PECL Output
80%
20%
0V Differential
V 0Y -
V 0Z
t
R
t
F
1.4 V
1.4 V
0V Differential
0V Differential
1.2 V C M
V0Z
1.2 V C M
V1B
V1A
V0Y
T
P LH
T
PHL
En1
En2
TPA
50
TPC
50
TPB
GND
150
150
Standard Termination
Pulse
Generator
A
B
10pF
VDD-2V
Figure 2. Differential Receiver to Driver Propagation Delay and Driver Transition Time
[3, 4, 5, 6, 7]
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