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參數(shù)資料
| 型號(hào)： | LTC2630CSC6-HZ10#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 8/22頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT R-R SC70-6 |
| 產(chǎn)品培訓(xùn)模塊： | LTC263x 12-, 10-, and 8-Bit VOUT DAC Family |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 3.9µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 480µW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-TSSOP，SC-88，SOT-363 |
| 供應(yīng)商設(shè)備封裝： | SC-70-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁(yè)面： | 1351 (CN2011-ZH PDF) |
| 其它名稱： | LTC2630CSC6-HZ10#TRMPBFDKR |
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LTC2630
16
2630ff
operation
Rail-to-Rail Output Considerations
Inanyrail-to-railvoltageoutputdevice,theoutputislimited
to voltages within the supply range.
SincetheanalogoutputoftheDACcannotgobelowground,
it may limit for the lowest codes as shown in Figure 4b.
Similarly, limiting can occur near full scale when using the
supply as reference. If VFS = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC, as shown in Figure 4. No full-scale limiting
can occur if VFS is less than VCC–FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Board Layout
ThePCboardshouldhaveseparateareasfortheanalogand
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane. The resistance from
the LTC2630 GND pin to the ground plane should be as
low as possible. Resistance here will add directly to the
effective DC output impedance of the device (typically
0.1Ω). Note that the LTC2630 is no more susceptible to
this effect than any other parts of this type; on the con-
trary, it allows layout-based performance improvements
to shine rather than limiting attainable performance with
excessive internal resistance.
Another technique for minimizing errors is to use a sepa-
rate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2630 is sinking large currents, this current flows
out the ground pin and directly to the power ground trace
without affecting the analog ground plane voltage.
It is sometimes necessary to interrupt the ground plane
to confine digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.
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