參數(shù)資料
型號(hào): COP8SGH044Q7
廠商: National Semiconductor Corporation
英文描述: LP38690/LP38692 1A Low Dropout CMOS Linear Regulators Stable with Ceramic Output Capacitors; Package: LLP; No of Pins: 6
中文描述: 8位的CMOS基于ROM和OTP微控制器具有8K到32K的內(nèi)存,2個(gè)比較器和USART
文件頁(yè)數(shù): 14/62頁(yè)
文件大?。?/td> 913K
代理商: COP8SGH044Q7
5.0 Functional Description (Continued)
5.11 CONTROL REGISTERS
CNTRL Register (Address X'00EE)
T1C3
T1C2
T1C1
T1C0
MSEL
IEDG
SL1
SL0
Bit 7
Bit 0
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
T1C3
Timer T1 mode control bit
T1C2
Timer T1 mode control bit
T1C1
Timer T1 mode control bit
T1C0
Timer T1 Start/Stop control in timer
modes 1 and
2,
T1
Underflow
Interrupt
Pending Flag in timer mode 3
MSEL
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
IEDG
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
PSW Register (Address X'00EF)
HC
C
T1PNDA
T1ENA
EXPND
BUSY
EXEN
GIE
Bit 7
Bit 0
The PSW register contains the following select bits:
HC
Half Carry Flag
C
Carry Flag
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1A capture
edge in mode 3)
T1ENA
Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
EXPND
External interrupt pending
BUSY
MICROWIRE/PLUS busy shifting flag
EXEN
Enable external interrupt
GIE
Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
Reserved
LPEN
T0PND
T0EN WPND
WEN
T1PNDB
T1ENB
Bit 7
Bit 0
The ICNTRL register contains the following bits:
Reserved This bit is reserved and must be zero
LPEN
L
Port
Interrupt
Enable
(Multi-Input
Wakeup/Interrupt)
T0PND
Timer T0 Interrupt pending
T0EN
Timer T0 Interrupt Enable (Bit 12 toggle)
WPND
MICROWIRE/PLUS interrupt pending
WEN
Enable MICROWIRE/PLUS interrupt
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
T1ENB
Timer T1 Interrupt Enable for T1B Input capture
edge
T2CNTRL Register (Address X'00C6)
T2C3
T2C2
T2C1
T2C0
T2PNDA
T2ENA
T2PNDB
T2ENB
Bit 7
Bit 0
The T2CNTRL control register contains the following bits:
T2C3
Timer T2 mode control bit
T2C2
Timer T2 mode control bit
T2C1
Timer T2 mode control bit
T2C0
Timer
T2
Start/Stop
control
in
timer
modes 1 and 2, T2 Underflow Interrupt Pend-
ing Flag in timer mode 3
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)
T2ENA
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-
ture edge
T2ENB
Timer T2 Interrupt Enable for Timer Underflow
or T2B Input capture edge
10131719
FIGURE 13. External Oscillator
10131720
For operation at lower than maximum R/C oscillator frequency.
10131721
For operation at maximum R/C oscillator frequency.
FIGURE 14. R/C Oscillator
COP8SG
Family
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相關(guān)PDF資料
PDF描述
COP8SGH044Q8 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
COP8SGH044Q9 LP38690/LP38692 1A Low Dropout CMOS Linear Regulators Stable with Ceramic Output Capacitors; Package: LLP; No of Pins: 6
COP8SGH044V3 LP38690-ADJ/LP38692-ADJ 1A Low Dropout CMOS Linear Regulators with Adjustable Output Stable with Ceramic Output Capacitors; Package: LLP; No of Pins: 6
COP8SGH044V6 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
COP8SGH044V7 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
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