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參數(shù)資料
| 型號(hào)： | CM6824IS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO |
| 中文描述： | 低啟動(dòng)電流式PFC / PWM控制器組合 |
| 文件頁(yè)數(shù)： | 12/18頁(yè) |
| 文件大?。?/td> | 342K |
| 代理商： | CM6824IS |
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CM6824
L
OW
S
TART-
U
P
C
URRENT
PFC/PWM C
ONTROLLER
C
OMBO
Oscillator (RAMP1)
The oscillator frequency is determined by the values of R
T
and C
T
, which determine the ramp and off-time of the
oscillator output clock:
1
+
The dead time of the oscillator is derived from the following
equation:
t
RAMP
= C
T
x R
T
x In
3.75
V
REF
at V
REF
= 7.5V:
t
RAMP
= C
T
x R
T
x 0.51
The dead time of the oscillator may be determined using:
t
DEADTIME
=
5.5mA
The dead time is so small (t
RAMP
>> t
DEADTIME
) that the
operating frequency can typically be approximately by:
1
2002/09/20
Preliminary
Rev. 1.1
Champion Microelectronic Corporation
Page 12
f
OSC
=
DEADTIME
RAMP
t
t
1.25
V
REF
2.5V
x C
T
= 450 x C
T
f
OSC
=
RAMP
t
EXAMPLE:
For the application circuit shown in the datasheet, with the
oscillator running at:
1
f
OSC
= 100kHz =
RAMP
t
Solving for C
T
x R
T
yields 1.96 x 10
-5
. Selecting standard
components values, C
T
= 390pF, and R
T
= 51.1k
The dead time of the oscillator adds to the Maximum PWM
Duty Cycle (it is an input to the Duty Cycle Limiter). With
zero oscillator dead time, the Maximum PWM Duty Cycle is
typically 45%. In many applications, care should be taken
that C
T
not be made so large as to extend the Maximum
Duty Cycle beyond 50%. This can be accomplished by
using a stable 390pF capacitor for C
T
.
PWM Section
Pulse Width Modulator
The PWM section of the CM6824 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing. The PWM is capable of current-mode or
voltage-mode operation. In current-mode applications, the
PWM ramp (RAMP2) is usually derived directly from a
current sensing resistor or current transformer in the
primary of the output stage, and is thereby representative
of the current flowing in the converter’s output stage.
DCI
LIMIT
, which provides cycle-by-cycle current limiting, is
typically connected to RAMP2 in such applications. For
voltage-mode, operation or certain specialized applications,
RAMP2 can be connected to a separate RC timing network
to generate a voltage ramp against which V
DC
will be
compared. Under these conditions, the use of voltage
feedforward from the PFC buss can assist in line regulation
accuracy and response. As in current mode operation, the
DC I
LIMIT
input is used for output stage overcurrent protection.
No voltage error amplifier is included in the PWM stage of
the CM6824, as this function is generally performed on the
output side of the PWM’s isolation boundary. To facilitate the
design of optocoupler feedback circuitry, an offset has been
built into the PWM’s RAMP2 input which allows V
DC
to
command a zero percent duty cycle for input voltages below
1.25V.
PWM Current Limit
The DC I
LIMIT
pin is a direct input to the cycle-by-cycle current
limiter for the PWM section. Should the input voltage at this
pin ever exceed 1V, the output flip-flop is reset by the clock
pulse at the start of the next PWM power cycle. Beside, the
cycle-by-cycle current, when the DC ILIMIT triggered the
cycle-by-cycle current, it also softly discharge the voltage of
soft start capacitor. It will limit PWM duty cycle mode.
Therefore, the power dissipation will be reduced during the
dead short condition.
V
IN
OK Comparator
The V
IN
OK comparator monitors the DC output of the PFC
and inhibits the PWM if this voltage on V
FB
is less than its
nominal 2.45V. Once this voltage reaches 2.45V, which
corresponds to the PFC output capacitor being charged to its
rated boost voltage, the soft-start begins.
PWM Control (RAMP2)
When the PWM section is used in current mode, RAMP2 is
generally used as the sampling point for a voltage
representing the current on the primary of the PWM’s output
transformer, derived either by a current sensing resistor or a
current transformer. In voltage mode, it is the input for a
ramp voltage generated by a second set of timing
components (R
RAMP2
, C
RAMP2
),that will have a minimum value
of zero volts and should have a peak value of approximately
5V. In voltage mode operation, feedforward from the PFC
output buss is an excellent way to derive the timing ramp for
the PWM stage.
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 20μA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed by
the following equation:
A
20
μ
C
SS
= t
DELAY
x
1.25V
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