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| 型號(hào)： | BU-61585G2-410Y |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| 封裝： | GULLWING PACKAGE-70 |
| 文件頁數(shù)： | 22/44頁 |
| 文件大?。?/td> | 563K |
| 代理商： | BU-61585G2-410Y |
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29
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
H1 web-09/02-0
Notes for FIGURE 15 and associated table.
1. For the 16-bit buffered nonzero wait configuration, TRANSPA-
RENT/BUFFERED must be connected to logic "0". ZERO_WAIT
and DTREQ/16/8 must be connected to logic "1". The inputs TRIG-
GER_SEL and MSB/LSB may be connected to either +5 V or
ground.
2. SELECT and STRBD may be tied together. IOEN goes low on
the first rising CLK edge when SELECT
STRBD is sampled low
(satisfying t1) and the BU-65170/61580's protocol/memory manage-
ment logic is not accessing the internal RAM. When this occurs,
IOEN goes low, starting the transfer cycle. After IOEN goes low,
SELECT may be released high.
3. MEM/REG must be presented high for memory access, low for
register access.
4. MEM/REG and RD/WR are buffered transparently until the first
falling edge of CLK after IOEN goes low. After this CLK edge,
MEM/REG and RD/WR become latched internally.
5. The logic sense for RD/WR in the diagram assumes that POLAR-
ITY_SEL is connected to logic "1." If POLARITY_SEL is connected
to logic "0," RD/WR must be asserted low to read.
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf
load. For loading above 50 pf, the validity of IOEN, READYD, and
D15-D0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. Timing for A15-A0, MEM/REG and SELECT assumes ADDR-LAT
is connected to logic "1." Refer to Address Latch timing for addition-
al details.
8. Internal RAM is accessed by A11 through A0 (A13 through A0 for
61585 and 61586). Registers are accessed by A4 through A0.
9. The address bus A15-A0 is internally buffered transparently until
the first rising edge of CLK after IOEN goes low. After this CLK
edge, A15-A0 become latched internally.
10. Setup time given for use in worst case timing calculations.
None of the ACE input signals are required to be synchronized to
the system clock. For ACE applications only, where SELECT and
STRBD do not meet the setup time of t1, but occur during the setup
window of an internal flip-flop, an additional clock cycle will be
inserted between the falling clock edge that latches MEM/REG and
RD/WR and the rising clock edge that latches the Address (A15-
A0). When this occurs, the pulse width of IOEN falling to READYD
falling (t11) increases by one clock cycle and the address hold time
(t10) must be increased be one clock cycle.
REF
DESCRIPTION
MIN
TYP
MAX
UNITS
NOTE REFERENCE
t1
SELECT and STRBD low setup time prior to clock rising edge
10
ns
notes 2, 10
t2
107.5
ns
notes 2, 6
t2
3.7
128.3
2.8
s
ns
s
notes 2, 6
t3
10
ns
notes 3, 4, 5, 7
t3
20
ns
notes 3, 4, 5, 7
t4
Address valid setup time following SELECT and STRBD low (@ 12 MHz)
Address valid setup time following SELECT and STRBD low (@ 16 MHz)
50
30
ns
t6
t5
SELECT hold time following IOEN falling
CLOCK IN rising edge delay to IOEN falling edge
0
35
ns
note 2
note 6
t9
t8
t7
Address valid setup time prior to CLOCK IN rising edge
MEM/REG, RD/WR hold time prior to CLOCK IN falling edge
MEM/REG, RD/WR setup time prior to CLOCK IN falling edge
30
10
ns
notes 7, 8, 9
notes 3, 4, 5, 7
t12
t11
t10
Output Data valid prior to READYD falling (@ 12 MHz)
Output Data valid prior to READYD falling (@ 16 MHz)
IOEN falling delay to READYD falling (reading registers @ 12 MHz)
IOEN falling delay to READYD falling (reading registers @ 16 MHz)
IOEN falling delay to READYD falling (reading RAM @ 12 MHz)
IOEN falling delay to READYD falling (reading RAM @ 16 MHz)
Address hold time following CLOCK IN rising edge
54
33
235
170
235
170
30
250
187.5
250
187.5
265
205
265
205
ns
note 6
notes 6, 10
notes 7, 8, 9, 10
SELECT and STRBD low delay to IOEN low (uncontended access @ 16 MHz)
SELECT and STRBD low delay to IOEN low (contended access @ 16 MHz)
SELECT and STRBD low delay to IOEN low (contended access @ 12 MHz)
SELECT and STRBD low delay to IOEN low (uncontended access @ 12 MHz)
MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 12 MHz)
TABLE FOR FIGURE 15. CPU READING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 16 MHz)
note 6
ns
35
CLOCK IN rising edge delay to READYD falling
t13
ns
∞
READYD falling to STRBD rising release time
t14
note 6
ns
30
STRBD rising edge delay to IOEN rising edge and READYD rising edge
t15
note 6
ns
0
Output Data hold time following STRBD rising edge
t16
ns
40
STRBD rising delay to output Data tri-state
t17
ns
0
STRBD high hold time from READYD rising
t18
ns
60
CLOCK IN rising edge delay to Output Data valid
t19
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