參數(shù)資料
型號： BU-61582G2-170Q
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
封裝： CERAMIC, GULL LEAD, 70 PIN
文件頁數(shù)： 36/48頁
文件大小： 378K
代理商： BU-61582G2-170Q
41
Data Device Corporation
www.ddc-web.com
BU-61582
G-08/02-250
16-bit bidirectional address bus. In both the buffered and transparent modes, the host CPU accesses the BU-61582 registers
and 16K words of internal RAM by A13 through A0. The host CPU performs register selection by A4 through A0. In the
buffered mode, A15-A0 are inputs only. In the transparent mode, A15-A0 are inputs during CPU accesses and drive outward
(towards the CPU) when the 1553 protocol/memory management logic accesses up to 64K x 16 of external RAM. The
address bus drives outward only in the transparent mode when the signal DTACK is low (indicating that the 61582 has control
of the processor interface bus) and IOEN is high (indicating that this is not a CPU access). Most of the time, including imme-
diately after power turn-on RESET, the A15-A0 outputs will be in their disabled (high impedance) state.
25
A10
A00
24
A01
23
A02
22
A03
A04
21
20
A05
17
A06
16
A07
15
A08
14
13
A09
12
A11
11
A12
10
A13
9
A14
8
A15 (MSB)
DESCRIPTION
PIN
SIGNAL NAME
SIGNAL DESCRIPTIONS, ADDRESS BUS (16)
SIGNAL NAME
PIN
DESCRIPTION
TX/RX-A (I/O)
-
PIN
TX/RX-A (I/O)
-
1
TX/RX-B (I/O)
-
2
TX/RX-B (I/O)
-
Analog Transmit/Receive Input/Outputs. Connect directly to 1553 isolation transformers.
34
35
X0* X1/X2*
Note: *Pin X0, X1/X2, X3, X6 refer to package option(X) and Voltage Transceiver option (0, 1, 2, 3, 6). See ordering information.
PIN
1
2
34
35
X3*
PIN
1
2
34
35
X6*
SIGNAL DESCRIPTIONS, 1553 ISOLATION TRANSFORMER INTERFACE (4)
相關PDF資料
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BU-61582G2-171S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
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