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參數(shù)資料
| 型號： | BU-61559D1-880L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| 封裝： | 45.70 X 53.30 MM, 5.30 MM HEIGHT, CERAMIC, DDIP-78 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 438K |
| 代理商： | BU-61559D1-880L |
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22
Data Device Corporation
www.ddc-web.com
BU-61559 Series
E-03/06-0
PROCESSOR INTERFACE TIMING
FIGURES 22 and 23 illustrate the timing for the host processor
to access the BU-61559's internal RAM in buffered mode. FIG-
URE 22 illustrates the buffered read cycle timing, while FIGURE
23 shows the buffered mode write cycle.
During a CPU transfer cycle, STRBD and SELECT must be sam-
pled low for two consecutive clock cycles when the BU-61559 is
not accessing the shared RAM. At this time, the output signals
IOEN and MEMENA-OUT are asserted low. IOEN is used to
enable external address and data tri-state buffers, if required.
MEMENA-IN is the Chip Select (CS) input to the BU-61559's
internal RAM. In the buffered mode, MEMENA-OUT must be
connected directly to MEMENA-IN. In the transparent mode, an
external address decoder may be used to provide MEMENA-IN,
as shown in FIGURE 20.
For a read cycle in the transparent mode, the output signal
MEMOE is asserted low one-half clock cycle after IOEN goes
low. MEMOE will remain low until the end of the read transfer
cycle. For a CPU write cycle in transparent mode, the output sig-
nal MEMWR is asserted low for one clock cycle (62.5 ns nomi-
nal), starting one clock cycle after IOEN is asserted low.
Three clock cycles (nominally 187.5 ns) after IOEN goes low, the
BU-61559 will assert the handshake output READYD low. This
informs the host processor that read data is available on D15-D0
or that write data has been stored. At this time, the CPU should
bring SELECT and STRBD high, completing the transfer cycle.
With two exceptions, the BU-61559 processor interface opera-
tion for accessing registers and internal RAM is essentially the
same for both the buffered and transparent interface modes. One
difference is the operation of the address latch/buffers, as
described under the preceding sub-heading. A second difference
is that for CPU accesses to external RAM in the transparent
mode, the data buffers remain in their high impedance state.
HARDWARE RESET (MSTCLR)
The MSTCLR control input to the BU-61559 provides a hardware
reset capability. A negative pulse of 50 ns or more will reset all
internal logic of the AIM-HY'er hybrid to its power turn-on or reset
idle state. In most systems, MSTCLR is connected to the host
processor's power turn-on RESET circuit.
BU-61559 INTERFACE TO STANAG 3910 HIGH-
SPEED PROTOCOL CHIP
STANAG 3910 HIGH-SPEED PROTOCOL CHIP
The 1553 BC/RT/MT is comprised of the DDC BU-61559 hybrid
and the two BUS-25679 transformers. In this interface, the BU-
61559 is configured in the transparent mode, interfacing to the
host processor by means of external data and address buffers.
This allows a STANAG 3910 High Speed Protocol Chip to moni-
tor all 1553 words being transferred over the BU-61559's paral-
lel data bus, D15-D00.
The STANAG 3910 remote terminal is comprised of a high-
speed RT protocol chip, data retiming unit, a 20 MHz fiber optic
transceiver, and RAM for high-speed messages. In some imple-
mentations, the data retiming unit and fiber optic transceiver may
be one component.
In general, The High Speed Protocol Chip operates by monitor-
ing the data bus, as well as various control signal outputs from
the BU-61559. The BU-61559 control signals that may be moni-
tored
include
BCSTRCV,
MSG_ERROR,
CMD_STR,
RXDTA_STR, TXDTA_STR, and MEMENA-OUT. The High
Speed Protocol Chip provides the MEMENA-IN input to the BU-
61559.
In the transparent interface mode, Command Words and High-
Speed Action Words may be monitored on the BU-61559's exter-
nal address and data buses. The High Speed Protocol Chip per-
forms all high-speed protocol operations, transmitting and
receiving messages over the 3910 fiber optic bus by means of
the data retiming unit and fiber optic transceiver.
When the BU-61559 receives a transmit command to the High-
Speed subaddress, the High Speed Protocol Chip captures the
Command Word. The High Speed Protocol Chip is then enabled
by the BU-61559's MEMENA-OUT and TXDTA_STR outputs to
provide the High-Speed Status, BIT, and Last Action words over
the BU-61559's data bus. When it does this, the High Speed
Protocol Chip presents the MEMENA-IN input to the BU-61559
high, de-selecting the BU-61559's internal (or possibly external)
RAM. The BU-61559 then responds over the 1553 (3838) bus
with the Data Words provided by the High Speed Protocol Chip.
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| BU-61580 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |ACE |
| BU-61580G1-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580G1-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580G1-120 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580G1-200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
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