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參數資料
| 型號： | ASM2I99446G-32-LR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2.5V and 3.3V LVCMOS Clock Distribution Buffer |
| 中文描述： | 99446 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, GREEN, LQFP-32 |
| 文件頁數： | 6/14頁 |
| 文件大小： | 575K |
| 代理商： | ASM2I99446G-32-LR |
July 2005
rev 0.4
ASM2I99446
2.5V and 3.3V LVCMOS Clock Distribution Buffer 6 of 14
Notice: The information in this document is subject to change without notice.
Table 9: AC CHARACTERISTICS
(V
CC
= V
CCA
= V
CCB
= V
CCC
= 2.5V ±5%, T
A
= –40°C to +85°C)
1,2
Symbol
f
ref
Characteristics
Min
0
0
0
1.4
2.6
2.6
Typ
Max
250
3
250
2
125
Unit
MHz
MHz
MHz
nS
nS
nS
nS
nS
nS
pS
pS
pS
nS
Condition
Input Frequency
FSELx=0
FSELx=1
0.7 to 1.7V
f
MAX
Maximum Output Frequency
÷1 output
÷2 output
CCLK0,1 to any Q
CCLK0,1 to any Q
t
P
,
REF
t
r
, t
f
t
PLH
t
PHL
t
PLZ,
HZ
t
PZL, LZ
Reference Input Pulse Width
CCLK Input Rise/Fall Time
1.0
4
5.6
5.5
10
10
Propagation delay
Output Disable Time
Output Enable Time
Output-to-output Skew
Within one bank
Any output Bank, Same output divider
Any output, Any output divider
Device-to-device Skew
Output pulse skew
5
t
sk(O)
150
200
350
3.0
t
sk(PP)
t
SK(P)
200
pS
DC
Q
t
r
, t
f
Note: 1 AC characteristics apply for parallel output termination of 50
to V
TT
.
2 AC specifications are design targets, final specification is pending device characterization.
3 The ASM2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.
4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
5 Output pulse skew is the absolute difference of the propagation delay times: | t
pLH
- t
pHL
|.
Output Duty Cycle
Output Rise/Fall Time
÷1 or ÷2 output
45
0.1
50
55
1.0
%
nS
DC
REF
= 50%
0.6 to 1.8V
Table 10: AC CHARACTERISTICS
(V
CC
= 3.3V + 5%, V
CCA
, V
CCB
, V
CCC
= 2.5V + 5% or 3.3V + 5%, T
A
= –40°C to +85°C)
1,2
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
t
sk(O)
Output-to-output Skew
Within one bank
Any output Bank, Same output divider
Any output, Any output divider
Device-to-device Skew
Propagation delay
Output pulse skew
3
150
250
350
2.5
pS
pS
pS
nS
t
sk(PP)
t
PLH,HL
CCLK0,1 to any Q
See 3.3V table
t
SK(P)
250
pS
DC
Q
Note: 1 AC characteristics apply for parallel output termination of 50
to V
TT
.
2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.
3 Output pulse skew is the absolute difference of the propagation delay times: | t
pLH
- t
pHL
|.
Output Duty Cycle
÷1 or ÷2 output
45
50
55
%
DC
REF
= 50%
相關PDF資料 |
PDF描述 |
|---|---|
| ASM2I99446G-32-LT | 2.5V and 3.3V LVCMOS Clock Distribution Buffer |
| ASM2I99447 | 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer |
| ASM2I99448G-32-ER | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448G-32-ET | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448G-32-LR | CAP CERM 470PF 500V X7R 10% 1206 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ASM2I99446G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V and 3.3V LVCMOS Clock Distribution Buffer |
| ASM2I99447 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer |
| ASM2I99448 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448-32-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| ASM2I99448-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
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