參數(shù)資料
型號: AS7C33512PFS32A-225TQC
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 512K X 32 STANDARD SRAM, 6.9 ns, PQFP100
封裝: 14 X 20 MM, TQFP-100
文件頁數(shù): 6/21頁
文件大?。?/td> 463K
代理商: AS7C33512PFS32A-225TQC
12/2/02, v. 0.9.8 Advance Info
Alliance Semiconductor
14 of 21
AS7C33512PFS32A
AS7C33512PFS36A
Identification register definitions
Scan register sizes
Instruction codes
Instruction field
512K x 36
Description
Revision number (31:28)
xxxx
Reserved for version number.
Device depth (27:23)
xxxxx/xxxxx
Defines the depth of 512K words.
Device width (22:18)
xxxxx/xxxxx
Defines the width of x32 or x36 bits.
Device ID (17:12)
xxxxxx
Reserved for future use.
JEDEC ID code (11:1)
00000110100 Allows unique identification of SRAM vendor.
ID register presence indicator (0)
1
Indicates the presence of an ID register.
Register name
Bit size
Instruction
3
Bypass
1
ID
32
Boundary scan
x18:53
x36:72
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high-Z state. This instruction is not 1149.1-compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high-Z state.
Reserved
011
Do not use. This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
Reserved
101
Do not use. This instruction is reserved for future use.
Reserved
110
Do not use. This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
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