參數(shù)資料
型號: AS7C31024B-12TCN
廠商: ALLIANCE MEMORY INC
元件分類: SRAM
英文描述: IC,AS7C31024B-12TCN,TSOP-32 I, SRAM,12NS,128K X 8,3.3V
中文描述: 128K X 8 STANDARD SRAM, 12 ns, PDSO32
封裝: 8 X 20 MM, LEAD FREE, TSOP1-32
文件頁數(shù): 6/9頁
文件大?。?/td> 120K
代理商: AS7C31024B-12TCN
AS7C31024B
3/24/04, v.1.2
Alliance Semiconductor
P. 6 of 9
Write waveform 2 (CE1 and CE2 controlled)10,11,12
AC test conditions
Notes
1
During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
2
This parameter is sampled and not 100% tested.
3
For test conditions, see AC Test Conditions, Figures A, and B.
4tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.
5
This parameter is guaranteed, but not 100% tested.
6WE is high for read cycle.
7CE1 and OE are low and CE2 is high for read cycle.
8
Address valid prior to or coincident with CE1 transition Low.
9
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11
All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
14 N/A
tAW
Address
CE1
WE
DOUT
tCW1, tCW2
tWP
tDW
tDH
tAH
tWC
tAS
CE2
Data valid
DIN
tWR
tWZ
255
– Output load: see Figure B.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
C13
320
DOUT
GND
+3.3V
168
Thevenin equivalent:
DOUT
+1.728V
Figure B: 3.3V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
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