參數(shù)資料
型號: AS7C1025B-15JCN
廠商: ALLIANCE MEMORY INC
元件分類: SRAM
英文描述: IC,AS7C1025B-15JCN,SOJ-32, SRAM,15NS,128K X 8,5V
中文描述: 128K X 8 STANDARD SRAM, 15 ns, PDSO32
封裝: 0.400 INCH, LEAD FREE, SOJ-32
文件頁數(shù): 6/9頁
文件大?。?/td> 397K
代理商: AS7C1025B-15JCN
AS7C1025B
Aug/09, v. 1.4
Alliance Memory Inc.
P. 6 of 9
Write waveform 2 (CE controlled)10,11
AC test conditions
Notes
1
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2
This parameter is sampled, but not 100% tested.
3
For test conditions, see AC Test Conditions, Figures A and B.
4tCLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±500 mV from steady-state voltage.
5
This parameter is guaranteed, but not 100% tested.
6
WE is high for read cycle.
7
CE and OE are low for read cycle.
8
Address is valid prior to or coincident with CE transition low.
9
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
tAW
Address
CE
WE
DOUT
tCW
tWP
tDW
tDH
tAH
tWZ
tWC
tAS
Data valid
DIN
tWR
– Output load: see Figure B.
– Input pulse level: GND to 3.5 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
168
Thevenin equivalent:
DOUT
+1.728 V
255
C13
480
DOUT
GND
+5 V
Figure B: 5 V Output load
10%
90%
10%
90%
GND
+3.5 V
Figure A: Input pulse
2 ns
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