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參數(shù)資料
| 型號： | AS7C1024B-20JIN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 5V 128K X 8 CMOS SRAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 20 ns, PDSO32 |
| 封裝： | 0.400 INCH, SOJ-32 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 111K |
| 代理商： | AS7C1024B-20JIN |
AS7C1024B
3/26/04, v 1.2
Alliance Semiconductor
P. 6 of 9
Write waveform 2 (CE1 and CE2 controlled)
10,11,12
AC test conditions
Notes
1
2
3
4
5
6
7
8
9
10 N/A
11
12 CE1 and CE2 have identical timing.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE1 is required to meet I
SB
specification.
This parameter is sampled and not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A and B.
t
CLZ
and t
CHZ
are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is high for read cycle.
CE1 and OE are low and CE2 is high for read cycle.
Address valid prior to or coincident with CE1 transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
t
AW
Address
CE1
WE
D
OUT
t
CW1
, t
CW2
t
WP
t
DW
Data valid
t
DH
t
AH
t
WR
t
WZ
t
WC
t
AS
CE2
D
IN
– Output load: see Figure B.
– Input pulse level: GND to 3.5V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
168
+1.728V
Thevenin equivalent:
D
OUT
255
C
13
480
D
OUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.5V
Figure A: Input pulse
2 ns
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| AS7C1024B-12STCN | 5V 128K X 8 CMOS SRAM |
| AS7C1024B-12STI | High Speed CMOS Logic Quad 2-Input NOR Gates 14-PDIP -55 to 125 |
| AS7C1024B-12STIN | High Speed CMOS Logic Quad 2-Input NOR Gates 14-PDIP -55 to 125 |
| AS7C1024B-12TC | High Speed CMOS Logic Quad 2-Input NOR Gates 14-SOIC -55 to 125 |
| AS7C1024B-12TCN | High Speed CMOS Logic Quad 2-Input NOR Gates 14-SOIC -55 to 125 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C1024B-20STC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-20STCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-20STI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-20STIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-20TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
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