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參數(shù)資料
| 型號： | AS7C1024B-15STCN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | High Speed CMOS Logic Quad 2-Input NAND Gates with Open Drain 14-PDIP -55 to 125 |
| 中文描述： | 128K X 8 STANDARD SRAM, 15 ns, PDSO32 |
| 封裝： | 8 X 13.40 MM, STSOP1-32 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 111K |
| 代理商： | AS7C1024B-15STCN |
AS7C1024B
3/26/04, v 1.2
Alliance Semiconductor
P. 4 of 9
Read cycle (over the operating range)
3,9,12
Parameter
Symbol
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
-10
-12
-15
-20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
10
-
-
-
-
3
3
3
-
-
0
–
0
–
Max
-
10
10
10
5
-
-
-
4
4
-
4
-
10
Min
12
–
–
–
–
3
3
3
–
–
0
–
0
–
Max
–
12
12
12
6
–
–
–
5
5
–
5
–
12
Min
15
–
–
–
–
3
3
3
–
–
0
–
0
–
Max
–
15
15
15
7
–
–
–
6
6
–
6
–
15
Min
20
–
–
–
–
3
3
3
–
–
0
–
0
–
Max
–
20
20
20
8
–
–
–
7
7
–
7
–
20
Read cycle time
Address access time
Chip enable (CE1) access time
Chip enable (CE2) access time
Output enable (OE) access time
Output hold from address change t
OH
CE1 Low to output in low Z
CE2 High to output in low Z
CE1 Low to output in high Z
CE2 Low to output in high Z
OE Low to output in low Z
OE High to output in high Z
Power up time
Power down time
3
3, 12
3, 12
5
t
CLZ1
t
CLZ2
t
CHZ1
t
CHZ2
t
OLZ
t
OHZ
t
PU
t
PD
4, 5, 12
4, 5, 12
4, 5, 12
4, 5, 12
4, 5
4, 5
4, 5, 12
4, 5, 12
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9,12
Read waveform 2 (CE1, CE2, and OE controlled)
3,6,8,9,12
Undefined / don’t care
Falling input
Rising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
supply
Current
CE2
OE
D
OUT
t
OE
t
OLZ
t
ACE1
,
tACE2
t
CHZ1
, t
CHZ2
t
CLZ1
, t
CLZ2
t
PU
t
PD
I
CC
I
SB
50%
50%
Data valid
t
RC1
CE1
t
OHZ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C1024B-15STI | High Speed CMOS Logic Quad 2-Input NAND Gates with Open Drain 14-SOIC -55 to 125 |
| AS7C1024B-15STIN | High Speed CMOS Logic Quad 2-Input NAND Gates with Open Drain 14-SOIC -55 to 125 |
| AS7C1024B-15TC | High Speed CMOS Logic Quad 2-Input NAND Gates with Open Drain 14-SOIC -55 to 125 |
| AS7C1024B-15TCN | High Speed CMOS Logic Quad 2-Input NAND Gates with Open Drain 14-SOIC -55 to 125 |
| AS7C1024B-15TI | High Speed CMOS Logic Quad 2-Input NAND Gates with Open Drain 14-SOIC -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C1024B-15STI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-15STIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-15TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-15TCN | 功能描述:靜態(tài)隨機(jī)存取存儲器 1M, 5V, 15ns FAST 128K x 8 Asynch 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| AS7C1024B-15TCNTR | 功能描述:靜態(tài)隨機(jī)存取存儲器 1M, 5V, 15ns FAST 128K x 8 Asynch 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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