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參數(shù)資料
| 型號： | AS7C1024B-10JCN |
| 廠商： | ALLIANCE MEMORY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 10 ns, PDSO32 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, SOJ-32 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 260K |
| 代理商： | AS7C1024B-10JCN |
AS7C1024B
3/26/04, v 1.2
Alliance Memory Inc.
P. 6 of 9
Write waveform 2 (CE1 and CE2 controlled)10,11,12
AC test conditions
Notes
1
During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
2
This parameter is sampled and not 100% tested.
3
For test conditions, see AC Test Conditions, Figures A and B.
4tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.
5
This parameter is guaranteed, but not 100% tested.
6WE is high for read cycle.
7CE1 and OE are low and CE2 is high for read cycle.
8
Address valid prior to or coincident with CE1 transition Low.
9
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
tAW
Address
CE1
WE
DOUT
tCW1, tCW2
tWP
tDW
tDH
tAH
tWZ
tWC
tAS
CE2
Data valid
DIN
tWR
– Output load: see Figure B.
– Input pulse level: GND to 3.5V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
168
Thevenin equivalent:
DOUT
+1.728V
255
C13
480
DOUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.5V
Figure A: Input pulse
2 ns
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| AS7C1024B-10STC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
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| AS7C1024B-10TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-10TCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-10TJC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
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