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參數(shù)資料
| 型號(hào)： | AS7C1024B-10JCN |
| 廠商： | ALLIANCE MEMORY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 10 ns, PDSO32 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, SOJ-32 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 260K |
| 代理商： | AS7C1024B-10JCN |
AS7C1024B
3/26/04, v 1.2
Alliance Memory Inc
P. 2 of 9
Functional description
The AS7C1024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8
bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for high
performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems.
When CE1 is high or CE2 is low, the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is
static, then full standby power is reached (ISB1). For example, the AS7C1024B is guaranteed not to exceed 55 mW under nominal full standby
conditions.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is
written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/
O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active,
output drivers stay in high-impedance mode.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Key: X = don’t care, L = low, H = high
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Vt1
–0.50
+7.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–1.0
W
Storage temperature (plastic)
Tstg
–65
+150
°
C
Ambient temperature with VCC applied
Tbias
–55
+125
°
C
DC current into outputs (low)
IOUT
–20
mA
Truth table
CE1
CE2
WE
OE
Data
Mode
H
X
High Z
Standby (ISB, ISB1)
X
L
X
High Z
Standby (ISB, ISB1)
L
H
High Z
Output disable (ICC)
LH
HL
DOUT
Read (ICC)
LHL
X
DIN
Write (ICC)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C1024LL-70TC | 128K X 8 STANDARD SRAM, 70 ns, PDSO32 |
| AS7C1025B-15JCN | IC,AS7C1025B-15JCN,SOJ-32, SRAM,15NS,128K X 8,5V |
| AS7C1026B-12TCN | IC,AS7C1026B-12TCN,TSOP-32 I, SRAM,12NS,64K X 16,5V |
| AS7C164-15JCN | IC,AS7C164-15JCN,SOJ-28 ASY SRAM,15NS,8K X 8,5V |
| AS7C164L-20JC | 8K X 8 STANDARD SRAM, 20 ns, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C1024B-10STC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-10STCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-10TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-10TCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
| AS7C1024B-10TJC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM |
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