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| 型號： | AS1539-BTST |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | ADC |
| 英文描述： | 10-bit, 8-CH, 50ksps ADC, I2C; Package Type: TSSOP-16; Temperature Range: -40 - +85 °C; Output Interface: I"C; Supply Voltage: 2,70-5,50 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 744K |
| 代理商： | AS1539-BTST |
www.austriamicrosystems.com
Revision 1.03
12 - 20
AS1539/AS1541
Data Sheet - Detailed Description
bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and
hold times must be taken into account. A master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the
data line HIGH to enable the master to generate the STOP condition.
Figure 24 on page 11
details how data transfer is accomplished on the I
2
C bus. Depending upon the state of the R/W
bit, two types of data transfer are possible:
-
Master Transmitter to Slave Receiver
. The first byte transmitted by the master is the slave address, followed by
a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte.
-
Slave Transmitter to Master Receiver
. The first byte, the slave address, is transmitted by the master. The slave
then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The
master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received
byte, a not-acknowledge is returned. The master device generates all of the serial clock pulses and the START
and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since a
repeated START condition is also the beginning of the next serial transfer, the bus will not be released.
The AS1539 can operate in the following slave modes:
-
Slave Receiver Mode
. Serial data and clock are received through SDA and SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial
transfer. Address recognition is performed by hardware after reception of the slave address and direction bit.
-
Slave Transmitter Mode
. The first byte (the slave address) is received and handled as in the slave receiver
mode. However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data is
transmitted on SDA by the AS1539 while the serial clock is input on SCL. START and STOP conditions are rec-
ognized as the beginning and end of a serial transfer.
Address Byte
The address byte
(see Figure 25)
is the first byte received following the START condition from the master device.
Figure 25. Address Byte
- The first five bits (MSBs) of the slave address are factory-set to 10010.
- The next two bits of the address byte are the device select bits, A1 and A0, which are set by the state of pins A1
and A0 at startup. A maximum of four devices with the same pre-set code can therefore be connected on the
same bus at one time. Pins A1/A0 can be connected to +V
DD
or digital ground.
- The last bit of the address byte (R/W) define the operation to be performed. When set to a 1 a read operation is
selected; when set to a 0 a write operation is selected.
Following the START condition, the AS1539 monitors the SDA bus, checking the device type identifier being transmit-
ted. Upon receiving the 10010 code, the appropriate device select bits, and the R/W bit, the slave device outputs an
acknowledge signal on the SDA line.
Command Byte
The AS1539/AS1541 operation, including powerdown
(see Table 5)
and channel selection
(see Table 6)
is determined
by a command byte
(see Figure 26)
.
Figure 26. Command Byte
1
0
0
1
0
A1
A0
R/W
MSB
6
5
4
3
2
1
LSB
SD
C2
C1
C0
PD1
PD0
X
X
MSB
6
5
4
3
2
1
LSB
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