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參數(shù)資料
| 型號(hào)： | AN610 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | PolarPAK Solder Joint Reliability Based on Thermal Fatigue IPC-9701 |
| 中文描述： | PolarPAK的焊點(diǎn)熱疲勞的可靠性基于IPC - 9701 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 1211K |
| 代理商： | AN610 |
www.vishay.com
2
Document Number 73507
31-Aug-05
Vishay Siliconix
AN610
DOE PHASE (I):
a) PCB design: A worst-case PCB design was se-
lected for this experiment, using a FR-4 board de-
signed with 16 layers and 3.175-mm [0.125-in.]
thickness as per IPC-9701 guidelines. Refer to the
Figure 3 for more information. The layer stack com-
prised two outer copper layers of 35 μm [0.5 oz.]
and 14 inner copper layers of 12 μm [0.5 oz.]. Each
insulation layer of the FR-4 in between is 231 μm
[7,709 μin.]. Appendix A covers the PCB specifica-
tions. For this experiment, an immersion silver
board finish was used as per recommendations
from external contract manufacturers.
The alternate signal, power, and ground plane from
both sides have 40%, 70%, and 70% copper cover-
age, respectively, on each layer. Horizontal and
vertical strips of controlled width and spacing deter-
mine the percentage of copper coverage. A con-
cept of a daisy chain layout for PolarPAK can be
followed from Figure 4.
The connection from the PCB termination enters
the right drain pin 4, where the first solder joint is
formed between the PCB and right drain pin. An
internal inverted cup structure connects two drain
pins. In turn, the daisy chain connection continues
to the second drain pin on the left side. The second
solder joint of the daisy chain is formed between the
left drain pin and the PCB. The daisy chain contin-
ues via a trace on the PCB to the gate - the second
pin from the left - where the third solder joint is
formed. A special modification on the part provides
an internal connection between the gate and
source pins. The fourth solder joint is formed at the
source, a large metal slug at the third pin from left,
and the PCB. A trace running out from the source
connection completes the daisy chain. When mon-
itoring the resistance of a daisy chain, all solder
joints of one PolarPAK device are studied for ther-
mal stress effects, including possible resulting sol-
der joint failures. Furthermore, the three white
square test pads shown in Figure 4 facilitate resis-
tance measurement of each solder joint.
The recommended minimum pad layout shown in
Figure 5 is used for the PCB layout. Refer to the
Vishay Web site for up-to-date information.
The dimensions of the PCB are governed by the
form factor required by the temperature cycling
setup. Accordingly, a 16-pin edge connector termi-
nation is used to facilitate the connection setup.
Figure 3: PCB Layer-Stack
Figure 4: Daisy Chain Layout for PolarPAK
TopL
a
yer
Core (7.709mil)
PT1 ((No Net))
Prepreg (10.0
3
1
S
T1
Core (7.709mil)
GT1 ((No Net))
Prepreg (10.0
3
1
S
T2
Core (7.709mil)
PT2 ((No Net))
Prepreg (10.0
3
1
S
T
3
Core (7.709mil)
GT2 ((No Net))
Prepreg (10.0
3
1
GB2 ((No Net))
Core (7.709mil)
S
B
3
Prepreg (10.0
3
PB2 ((No Net))
Core (7.709mil)
S
B2
Prepreg (10.0
3
1
GB1 ((No Net))
Core (7.709mil)
S
B1
Prepreg (10.0
3
1
PB1 ((No Net))
Core (7.709mil)
BottomL
a
yer
Figure 5: Recommended Minimum Pad Layout
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