
ICs for TV
AN5829S
5
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Stereo separation (100%)-1
Sep
100-1
f
=
300 Hz, (L(R)-only) 100
%
mod
f
=
1 kHz, (L(R)-only) 100
%
mod
f
=
3 kHz, (L(R)-only) 100
%
mod
f
=
8 kHz, (L(R)-only) 100
%
mod
f
=
300 Hz, (L(R)-only) 30
%
mod
f
=
1 kHz, (L(R)-only) 30
%
mod
f
=
3 kHz, (L(R)-only) 30
%
mod
f
=
8 kHz, (L(R)-only) 30
%
mod
f
=
300 Hz, (L(R)-only) 10
%
mod
f
=
1 kHz, (L(R)-only) 10
%
mod
f
=
3 kHz, (L(R)-only) 10
%
mod
f
=
8 kHz, (L(R)-only) 10
%
mod
20
35
dB
Stereo separation (100%)-2
Sep
100-2
17
28
dB
Stereo separation (100%)-3
Sep
100-3
20
35
dB
Stereo separation (100%)-4
Sep
100-4
10
18
dB
Stereo separation (30%)-1
Sep
30-1
22
35
dB
Stereo separation (30%)-2
Sep
30-2
20
35
dB
Stereo separation (30%)-3
Sep
30-3
22
35
dB
Stereo separation (30%)-4
Sep
30-4
14
22
dB
Stereo separation (10%)-1
Sep
10-1
20
35
dB
Stereo separation (10%)-2
Sep
10-2
20
35
dB
Stereo separation (10%)-3
Sep
10-3
20
30
dB
Stereo separation (10%)-4
Sep
10-4
14
22
dB
I
2
C interface
Bus free before start
t
BUF
4.0
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
Start condition set-up time
t
SU.STA
4.0
Start condition hold time
t
HD.STA
4.0
Low period SCL, SDA
t
LO
4.0
High period SCL
t
HI
4.0
Rise time SCL, SDA
t
r
1.0
Fall time SCL, SDA
t
f
0.35
Data set-up time (write)
t
SU.DAT
0.25
Data hold time (write)
t
HD.DAT
0.3
Acknowledge set-up time
t
SU.ACK
3.5
Acknowledge hold time
t
HD.ACK
0
Stop condition set-up time
t
SU.STO
4.0
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
AGC gain 1
*1
V
AGC1
f
=
1 kHz, V
IN(EXT)
=
50 mV[rms]
f
=
1 kHz, V
IN(EXT)
=
500 mV[rms]
67
100
140
mV[rms]
AGC gain 2
*1
V
AGC2
180
270
390
mV[rms]
I
2
C interface
Sink current at ACK
I
ACK
Maximum pin 2 sink current at ACK
1
2
20
mA
SCL, SDA signal input high level
V
IHI
3.5
5.0
V
SCL, SDA signal input low level
V
ILO
0
0.9
V
Input available maximum frequency
f
Imax
100
kbit/s
I
Electrical Characteristics at V
CC
=
5 V, NR: On,T
a
=
25
°
C (continued)
Note)*1: 00H register: D7
=
0, D6
=
1
Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.