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參數(shù)資料
| 型號： | AN5829S |
| 廠商： | PANASONIC CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Sound multiplex decoder IC for the U.S. televisions |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO24 |
| 封裝： | 0.375 INCH, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 131K |
| 代理商： | AN5829S |
ICs for TV
AN5829S
13
0
1
1
0
6
1
0
1
1
B
0
0
1
0
2
0
0
0
0
0
0
0
0
0
0
1
0
0
0
8
SDA
SCL
Start
condition
Slave
address
Acknowledge
bit
Acknowledge
bit
Acknowledge
bit
Data
Stop
condition
Sub
address
I
Technical Information
[1] I
2
C bus
1. Receiving mode
Transmission message
As transfer messages, SCL and SDA are transfered synchronouslly and serially. SCL is a constant clock
frequency and SDA is address data for controlling a receiving side and is sent in parallel by synchronizing with
SCL. Data are in principle sent by 8-bit 3-octet (byte) and there exists an acknowledge bit per octet. The frame
structure is mentioned below:
1) Start condition
When SDA becomes from high to low at SCL
=
high, the receiver gets ready to receive.
2) Stop condition
When SDA becomes from low to high at SCL
=
high, the receiver stops receiving.
3) Slave address
Specified for each device. If any addresses of other devices are sent, receiving will be stopped.
4) Sub-address
Specified for each function.
5) Data
Data for controlling
6) Acknowledge bit
This is the bit that informs the master of data reception every octet. The master sends the high signal and
the receiver sends back the low signal as shown with the dotted line in the above figure, thus the master
acknowledges reception on the receiver side. If the low signal is not sent back, the reception will be stopped.
Except for the start and stop conditions, SDA does not change at SCL
=
high.
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