參數(shù)資料
型號: ADT7473ARQZ-1REEL
廠商: ANALOG DEVICES INC
元件分類: 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 2.50Cel, RECTANGULAR, SURFACE MOUNT
封裝: ROHS COMPLIANT, MO-137AB, QSOP-16
文件頁數(shù): 66/72頁
文件大?。?/td> 1494K
代理商: ADT7473ARQZ-1REEL
ADT7473/ADT7473-1
Rev. C | Page 69 of 72
Table 56. Register 0x78—Configuration Register 3 (Power-On Default = 0x00)
Bit
Name
R/W1
Description
[0]
ALERT
Enable
R/W
ALERT = 0 (default), ADT7473 Pin 5 is configured as PWM2.
ALERT = 1, Pin 5 for ADT7473 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to
indicate out-of-limit error conditions.
ALERT = 0 (default), ADT7473-1 Pin 5 is configured as THERM_LATCH.
ALERT = 1, Pin 5 for ADT7473-1 (THERM_LATCH/PWM2) is configured as PWM2
[1]
THERM
R/W
THERM Enable = 1 enables THERM functionality on Pin 9. Also determined by Bit 0 and Bit 1 (PIN9FUNC) of
Configuration Register 4. Direction is controlled by Bit 5, Bit 6, and Bit 7 of Configuration Register 5 (0x7C).
When THERM is asserted, if the fans are running and the boost bit is set, the fans run at full speed. THERM
can also be programmed so that a timer monitors the duration THERM has been asserted.
[2]
BOOST
R/W
When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum
programmed duty cycle for fail-safe cooling.
[3]
FAST
R/W
FAST = 1, enables fast TACH measurements on all channels. This increases the TACH measurement rate
from once per second to once every 250 ms (4 ×).
[4]
DC1
R/W
DC1 = 1, enables TACH measurements to be continuously made on TACH1. Fans must be driven by dc.
Setting this bit prevents pulse stretching because it is not required for dc-driven motors.
[5]
DC2
R/W
DC2 = 1, enables TACH measurements to be continuously made on TACH2. Fans must be driven by dc.
Setting this bit prevents pulse stretching because it is not required for dc-driven motors.
[6]
DC3
R/W
DC3 = 1, enables TACH measurements to be continuously made on TACH3. Fans must be driven by dc.
Setting this bit prevents pulse stretching because it is not required for dc-driven motors.
[7]
DC4
R/W
DC4 = 1, enables TACH measurements to be continuously made on TACH4. Fans must be driven by dc.
Setting this bit prevents pulse stretching because it is not required for dc-driven motors.
1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 57. Register 0x79—THERM Timer Status Register (Power-On Default = 0x00)
Bit
Name
R/W
Description
[7:1]
TMR
Read-only
Times the duration THERM input is asserted. These seven bits read 0 until the THERM assertion time
exceeds 45.52 ms.
[0]
ASRT/
TMR0
Read-only
This bit is set high on the assertion of the THERM input, and is cleared on read. If the THERM assertion time
exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This allows THERM assertion
times from 45.52 ms to 5.82 seconds to be reported back with a resolution of 22.76 ms.
Table 58. Register 0x7A—THERM Timer Limit Register (Power-On Default = 0x00)
Bit
Name
R/W
Description
[7:0]
LIMT
R/W
Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8-bit limit
with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 seconds to be
programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status Register 2
(Reg. 0x42) is set. If the limit value is 0x00, an interrupt is generated immediately on the assertion of
the THERM input.
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