參數(shù)資料
型號: ADT7473ARQZ-1REEL
廠商: ANALOG DEVICES INC
元件分類: 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 2.50Cel, RECTANGULAR, SURFACE MOUNT
封裝: ROHS COMPLIANT, MO-137AB, QSOP-16
文件頁數(shù): 22/72頁
文件大?。?/td> 1494K
代理商: ADT7473ARQZ-1REEL
ADT7473/ADT7473-1
Rev. C | Page 29 of 72
includes a fan start-up timeout function. During this time, the
ADT7473/ADT7473-1 looks for two TACH pulses. If two
TACH pulses are not detected, an interrupt is generated. Using
Configuration Register 1 (0x40), Bit 5 (FSPDIS), this function-
ality can be changed (see the Disabling Fan Startup Timeout
section).
PWM1, PWM2, PWM3 Configuration Registers
(Register 0x5C, Register 0x5D, and Register 0x5E)
Bits [2:0] SPIN, start-up timeout for PWM1 = 0x5C,
PWM2 = 0x5D, and PWM3 = 0x5E.
000 = No start-up timeout
001 = 100 ms
010 = 250 ms default
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
Disabling Fan Startup Timeout
Although fan start-up makes fan spin-ups much quieter than
fixed-time spin-ups, the option exists to use fixed spin-up
times. Setting Bit 5 (FSPDIS) to 1 in Configuration Register 1
(0x40) disables the spin-up for two TACH pulses. Instead, the
fan spins up for the fixed time as selected in Register 0x5C to
Register 0x5E.
PWM Logic State
The PWM outputs can be programmed high for a 100% duty
cycle (noninverted) or low for a 100% duty cycle (inverted).
PWM1 Configuration Register (0x5C)
Bit 4 INV.
0 = Logic high for a 100% PWM duty cycle
1 = Logic low for a 100% PWM duty cycle
PWM2 Configuration Register (0x5D)
Bit 4 INV.
0 = Logic high for a 100% PWM duty cycle
1 = Logic low for a 100% PWM duty cycle
PWM3 Configuration Register (0x5E)
Bit 4 INV.
0 = Logic high for a 100% PWM duty cycle
1 = Logic low for a 100% PWM duty cycle
Low Frequency Mode PWM Drive Frequency
The PWM drive frequency can be adjusted for the application.
Register 0x5F to Register 0x61 configure the PWM frequency
for PWM1 to PWM3, respectively. In high frequency mode, the
PWM drive frequency is always 22.5 kHz.
High Frequency Mode PWM Drive
Setting Bit 3 of Register 0x5F, 60H or 61H enables high
frequency mode for fans 1, 2 and 3.
PWM Frequency Registers (Register 0x5F to
Register 0x61)
Bits [2:0] FREQ
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
Fan Speed Control
The ADT7473/ADT7473-1 controls fan speed using automatic
and manual modes.
In automatic fan speed control mode, fan speed is automatically
varied with temperature and without CPU intervention, once
initial parameters are set up. The advantage of this is that, if the
system hangs, the user is guaranteed the system is protected
from overheating. The automatic fan speed control incorporates
a feature called dynamic TMIN calibration. This feature reduces
the design effort required to program the automatic fan speed
control loop. For more information and procedures on how to
program the automatic fan speed control loop and dynamic
TMIN calibration, see the Programming the Automatic Fan Speed
In manual fan speed control mode, the ADT7473/ADT7473-1
allows the duty cycle of any PWM output to be manually
adjusted. This can be useful if the user wants to change fan
speed in software or adjust the PWM duty cycle output for
test purposes. Bits [7:5] of Register 0x5C to Register 0x5E
(PWM configuration registers) control the behavior of each
PWM output.
PWM Configuration Registers (Register 0x5C to
Register 0x5E)
Bits [7:5] BHVR
111 = manual mode
Once under manual control, each PWM output can be manu-
ally updated by writing to Register 0x30 to Register 0x32 (PWM
current duty cycle registers).
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8-bit registers that
allow the PWM duty cycle for each output to be set anywhere
from 0% to 100% in steps of 0.39%.
The value to be programmed into the PWMMIN register is given by
Value (decimal) = PWMMIN/0.39
Example 1
For a PWM duty cycle of 50%
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 0x80 (hex)
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