參數(shù)資料
型號： ADSP-BF535PBB-300
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： Blackfin Embedded Processor
中文描述： 32-BIT, 40 MHz, OTHER DSP, PBGA260
封裝： PLASTIC, MS-034AAG-1, BGA-260
文件頁數(shù)： 36/44頁
文件大?。?/td> 1388K
代理商： ADSP-BF535PBB-300
ADSP-BF535
–36–
REV. A
Output Drive Currents
Figure 19
through
Figure 21
show typical current-voltage char-
acteristics for the output drivers of the ADSP-BF535 Blackfin
processor. The curves represent the current drive capability of
the output drivers as a function of output voltage.
Figure 19
applies to the
ABE3–0
, SDQM3–0, ADDR25–2,
AMS3–0
,
AOE
,
ARE
,
AWE
, CLKOUT, SCLK1, DATA31–0, DT1–0,
EMU
, MISO1–0, MOSI1–0, PF15–0, RFS1–0, RSCLK1–0,
SA10,
SCAS
, SCK1–0, SCKE, SCLK0, DEEPSLEEP,
SMS3–0
,
SRAS
, SUSPEND,
SWE
, TDO, TFS1–0, TMR2–0,
TSCLK1–0, TX1–0, TXDMNS, TXDPLS,
TXEN
, and
XTAL0 pins.
Figure 20
applies to the PCI_AD31–0,
PCI_CBE3–0
,
PCI_DEVSEL
,
PCI_FRAME
,
PCI_INTA
,
PCI_IRDY
, PCI_PAR,
PCI_PERR
,
PCI_RST
,
PCI_SERR
,
PCI_STOP
, and
PCI_TRDY
pins.
Figure 21
applies to the
PCI_REQ
pin.
Power Dissipation
Total power dissipation has two components: one due to internal
circuitry (P
INT
) and one due to the switching of external output
drivers (P
EXT
).
Table 26
shows the power dissipation for internal
circuitry (V
DDINT
). Internal power dissipation is dependent on the
instruction execution sequence and the data operands involved.
Table 27
shows the power dissipation for the phase-locked loop
(PLL) circuitry (V
DDPLL
).
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
Maximum frequency (f
0
) at which all output pins can
switch during each cycle
Their load capacitance (C
0
) of all switching pins
Their voltage swing (V
DDEXT
)
The external component is calculated using:
Figure 19. Output Drive Current
Figure 20. PCI 33 MHz Output Drive Current
200
150
100
50
0
100
150
200
50
V
OH
(V
DDEXT
= 3.45V,
40°C)
V
OH
(V
DDEXT
= 3.45V, 0°C)
V
OH
(V
DDEXT
= 3.3V, +25°C)
V
OH
(V
DDEXT
= 3.15V, +105°C)
V
OH
(V
DDEXT
= 2.5V, +85°C)
V
OL
(V
DDEXT
= 3.3V, +25°C)
V
OL
(V
DDEXT
= 2.5V, +85°C)
V
OL
(V
DDEXT
= 3.45V, 0°C)
V
OL
DDEXT
= 3.45V,
V
OL
(V
DDEXT
= 3.15V, +105°C)
40°C)
SOURCE (V
O
) VOLTAGE – V
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
4.0
S
O
)
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
4.0
200
150
100
50
0
50
100
150
OH
(V
DDEXT
= 3.3V, +25°C)
V
OH
(V
DDEXT
= 3.15V, +105°C)
V
OH
(V
DDEXT
= 2.5V,
+85°C)
V
OH
DDEXT
= 3.45V, 0°C)
V
OH
(V
DDEXT
= 3.45V,
45°C)
V
OL
(V
DDEXT
= 3.3V, +25°C)
V
OL
(V
DDEXT
= 2.5V, +85°C)
V
OL
(V
DDEXT
= 3.45V, 0°C)
OL
(V
DDEXT
= 3.15V, +105°C)
V
OL
(V
DDEXT
= 3.45V,
45°C)
S
O
)
SOURCE (V
O
) VOLTAGE – V
200
250
300
Figure 21. PCI_REQ Output Drive Current
Table 26. Internal Power Dissipation
Test Conditions
1
f
CCLK
=
100 MHz
V
DDINT
=
1.0 V
96.0
114.0
15.0
1
I
DD
data is specified for typical process parameters. All data at 25oC.
2
Processor executing 75% dual Mac, 25% ADD with moderate data bus
activity.
3
Implementation of Enhanced Full Rate (EFR) GSM algorithm.
4
See the
ADSP-BF535 Blackfin Processor Hardware Reference Manual
for
definitions of Sleep and Deep Sleep operating modes.
5
I
DD
is specified for when the device is in the reset state.
Parameter
I
DDTYP
2
I
DDEFR
3
I
DDSLEEP
4
I
DDDEEPSLEEP
4
4.0
I
DDRESET
5
f
CCLK
=
200 MHz
V
DDINT
=
1.2 V
206.0
248.0
29.0
5.0
255.0
f
CCLK
=
300 MHz
V
DDINT
=
1.5 V
387.0
463.0
52.0
8.2
485.3
f
CCLK
=
350 MHz
V
DDINT
=
1.6 V
498.0
579.0
62.0
9.8
651.0
Unit
mA
mA
mA
mA
mA
132.0
SOURCE (V
O
) VOLTAGE – V
S
O
)
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
4.0
200
150
100
50
0
50
100
150
200
V
OH
(V
DDEXT
= 3.3V, +25°C)
V
OH
(V
DDEXT
= 3.15V,
V
OH
(V
DDEXT
= 2.5V, +85°C)
V
OH
(V
DDEXT
= 3.45V, 0°C)
+105°C)
V
OH
(V
DDEXT
= 3.45V,
45°C)
V
OL
(V
DDEXT
= 3.3V, +25°C)
V
OL
(V
DDEXT
= 2.5V, +85°C)
V
OL
(V
DDEXT
= 3.45V, 0°C)
V
OL
DDEXT
= 3.45V,
V
OL
(V
DDEXT
= 3.15V, +105°C)
45°C)
P
EXT
V
DDEXT
2
C
0
f
0
×
∑
×
=
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