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參數(shù)資料
| 型號： | ADSP-21362KBC-1AA |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數(shù)： | 31/52頁 |
| 文件大?。?/td> | 1320K |
| 代理商： | ADSP-21362KBC-1AA |
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. A
|
Page 31 of 52
|
December 2006
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, data channel A, data channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 26. Serial Ports—External Clock
Parameter
Timing Requirements
t
SFSE
1
Min
Max
Unit
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
SCLK Width
SCLK Period
2.5
ns
t
HFSE
1
2.5
2.5
2.5
12
24
ns
ns
ns
ns
ns
t
SDRE
1
t
HDRE
1
t
SCLKW
t
SCLK
Switching Characteristics
t
DFSE
2
FS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
9.5
ns
t
HOFSE
2
2
ns
ns
ns
t
DDTE
2
t
HDTE
2
9.5
2
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 27. Serial Ports—Internal Clock
Parameter
Timing Requirements
t
SFSI
1
Min
Max
Unit
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
7
ns
t
HFSI
1
2.5
7
2.5
ns
ns
ns
t
SDRI
1
t
HDRI
1
Switching Characteristics
t
DFSI
2
t
HOFSI
2
t
DFSIR
2
t
HOFSIR
2
t
DDTI
2
t
HDTI
2
t
SCLKIW
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
FS Delay After SCLK (Internally Generated FS in Receive Mode)
FS Hold After SCLK (Internally Generated FS in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit or Receive SCLK Width
3
ns
ns
ns
ns
ns
ns
ns
–1.0
8
–1.0
3
–1.0
0.5t
SCLK
– 2
0.5t
SCLK
+ 2
1
Referenced to the sample edge.
2
Referenced to drive edge.
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| ADSP-21362KBCZ-1AA | SHARC Processor |
| ADSP-21362WBBCZ-1A | SHARC Processor |
| ADSP-21363BBC-1AA | SHARC Processor |
| ADSP-21363BBCZ-1AA | SHARC Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADSP-21362KBCZ-1AA | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21362KSWZ-1AA | 制造商:Analog Devices 功能描述:IC SHARC DSP 333MHZ SMD LQFP144 |
| ADSP-21362WBBCZ-1A | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21362YSWZ-2AA | 功能描述:IC DSP 32BIT 200MHZ EPAD 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21363 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
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