參數資料
型號： DSPIC33FJ16GP304T-I/PT
廠商： Microchip Technology
文件頁數： 31/176頁
文件大小： 0K
描述： IC DSPIC MCU/DSP 16K 44TQFP
產品培訓模塊： Asynchronous Stimulus
標準包裝： 1,200
系列： dsPIC™ 33F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 40 MIP
連通性： I²C，IrDA，LIN，SPI，UART/USART
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數： 35
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數據轉換器： A/D 13x12b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 帶卷 (TR)
配用： DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱： DSPIC33FJ16GP304T-I/PTTR
124
AT89C5131
4136C–USB–04/05
Bulk/Interrupt IN Transactions
in Ping-pong Mode
Figure 62. Bulk/Interrupt IN Transactions in Ping-pong Mode
An endpoint will be first enabled and configured before being able to send Bulk or Inter-
rupt packets.
The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in
the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the
next IN request concerning the endpoint. The FIFO banks are automatically switched,
and the firmware can immediately write into the endpoint FIFO bank 1.
When the IN packet concerning the bank 0 has been sent and acknowledged by the
Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if
enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO bank 0
with new data. The FIFO banks are then automatically switched.
When the IN packet concerning the bank 1 has been sent and acknowledged by the
Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if
enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO bank 1
with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by
the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,
the USB controller will answer a NAK handshake for each IN requests concerning this
bank.
Note that in the example above, the firmware clears the Transmit Complete bit (TXC-
MPL) before setting the Transmit Ready bit (TXRDY). This is done in order to avoid the
firmware to clear at the same time the TXCMPL bit for bank 0 and the bank 1.
The firmware will never write more bytes than supported by the endpoint FIFO.
IN
DATA0 (n Bytes)
ACK
HOST
UFI
C51
Endpoint FIFO Bank 0 - Write Byte 1
IN
NACK
TXCMPL
Endpoint FIFO Bank 0 - Write Byte 2
Endpoint FIFO Bank 0 - Write Byte n
Set TXRDY
Endpoint FIFO Bank 1 - Write Byte 1
Endpoint FIFO Bank 1 - Write Byte 2
Endpoint FIFO Bank 1 - Write Byte m
Set TXRDY
IN
DATA1 (m Bytes)
ACK
Endpoint FIFO Bank 0 - Write Byte 1
Endpoint FIFO Bank 0 - Write Byte 2
Endpoint FIFO Bank 0 - Write Byte p
Set TXRDY
Clear TXCMPL
IN
DATA0 (p Bytes)
ACK
TXCMPL
Clear TXCMPL
Endpoint FIFO Bank 1 - Write Byte 1
相關PDF資料
PDF描述
P51-300-A-Y-D-4.5V-000-000 SENSOR 300PSI 7/16-20-2B .5-4.5V
P51-15-G-UCA-MD-5V-000-000 SENSOR 15PSI 7/16-20UNF 1-5V
P51-50-S-H-P-20MA-000-000 SENSOR 50PSIS M12 4-20 MA
P51-1000-A-S-D-4.5OVP-000-000 SENSOR 1000PSI 1/4-18NPT .5-4.5V
DSPIC33FJ32GP202T-I/SO IC DSPIC MCU/DSP 32K 28SOIC
相關代理商/技術參數
參數描述
ADS1259EVM 功能描述:數據轉換 IC 開發(fā)工具 ADS1259 Eval Mod RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
ADS1259EVM 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL
ADS1259EVM-PDK 功能描述:數據轉換 IC 開發(fā)工具 ADS1259 Perf Demo Kit RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
ADS1259EVM-PDK 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL
ADS1259IPW 功能描述:模數轉換器 - ADC Low-Noise 14kSPS 24B ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯系方式

*
*
*