參數(shù)資料
型號: ADC1112D125HN
廠商: NXP Semiconductors N.V.
元件分類: 外設及接口
英文描述: Dual 11-bit ADC; CMOS or LVDS DDR digital outputs
封裝: ADC1112D125HN/C1<SOT804-3|<<<1<Always Pb-free,;ADC1112D125HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 30/41頁
文件大?。?/td> 565K
代理商: ADC1112D125HN
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11.6.3
Register allocation map
A
A
P
R
3
N
A
D
Table 19.
Address
(hex)
Register allocation map
Register name
Access
Bit definition
Bit 3
Default
(bin)
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED[5:0]
Bit 2
Bit 1
ADCB
OP_MODE[1:0]
Bit 0
ADCA
0003
0005
Channel index
Reset and
operating mode
Clock
Internal reference R/W
Output data
standard.
Output clock
Offset
Test pattern 1
Test pattern 2
Test pattern 3
Fast OTR
CMOS output
LVDS DDR O/P 1 R/W
LVDS DDR O/P 2 R/W
R/W
R/W
1111 1111
0000 0000
SW_
RST
-
-
-
RESERVED[2:0]
-
-
0006
0008
0011
R/W
-
-
-
-
-
-
SE_SEL
-
LVDS_
CMOS
-
DIFF_SE
INTREF_EN
OUTBUF
RESERVED
CLKDIV
DCS_EN 0000 0001
0000 0000
0000 0000
INTREF[2:0]
DATA_FORMAT[1:0]
R/W
OUTBUS_SWAP
0012
0013
0014
0015
0016
0017
0020
0021
0022
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
DAVINV
DIG_OFFSET[5:0]
-
TESTPAT_USER[10:3]
-
FASTOTR
DAV_DRV[1:0]
DAVI[1:0]
BIT_BYTE_WISE
DAVPHASE[2:0]
0000 1110
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 1110
0000 0000
0000 0000
-
-
TESTPAT_SEL[2:0]
TESTPAT_USER[2:0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FASTOTR_DET[2:0]
DATA_DRV[1:0]
DATAI[1:0]
RESERVED
-
RESERVED
-
LVDS_INT_TER[2:0]
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