參數(shù)資料
型號: AD9517-4ABCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 20/80頁
文件大小: 0K
描述: IC CLOCK GEN 1.8GHZ VCO 48LFCSP
設計資源: High Performance, Dual Channel IF Sampling Receiver (CN0140)
標準包裝: 750
類型: 時鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:12
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.8GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應商設備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
Data Sheet
AD9517-4
Rev. E | Page 27 of 80
DETAILED BLOCK DIAGRAM
PROGRAMMABLE
N DELAY
REFIN (REF1)
REFIN (REF2)
CLK
REF1
REF2
AD9517-4
STATUS
R
DIVIDER
VCO STATUS
PROGRAMMABLE
R DELAY
REFERENCE
SWITCHOVER
REF_ SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
VCO
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PL
L
RE
F
E
RE
NC
E
HOLD
OUT0
OUT1
OUT0
OUT1
LVPECL
DIVIDE BY
1 TO 32
OUT2
OUT3
OUT2
OUT3
LVPECL
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LVDS/CMOS
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LVDS/CMOS
DIVIDE BY
1 TO 32
0
1
DIVIDE BY
2, 3, 4, 5, OR 6
PD
SYNC
RESET
SCLK
SDIO
SDO
CS
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
T
0
64
28
-00
2
Figure 42. Detailed Block Diagram
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