參數(shù)資料
型號： AD9445-BB-PCB
廠商： Analog Devices, Inc.
英文描述： 14-Bit, 105/125 MSPS, IF Sampling ADC
中文描述： 14位，一百二十五分之一百○五MSPS的，中頻采樣ADC
文件頁數(shù)： 28/40頁
文件大小： 965K
代理商： AD9445-BB-PCB
AD9445
OPERATIONAL MODE SELECTION
Data Format Select
The data format select (DFS) pin of the AD9445 determines
the coding format of the output data. This pin is 3.3 V CMOS-
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement and DFS logic low (AGND) selecting offset binary
format. Table 10 summarizes the output coding.
Rev. 0 | Page 28 of 40
Output Mode Select
The OUPUT MODE pin controls the logic compatibility, as well
as the pinout of the digital outputs. This pin is a CMOS-compatible
input. With OUTPUT MODE = 0 (AGND), the AD9445 outputs
are CMOS compatible, and the pin assignment for the device is
as defined in Table 8. With OUTPUT MODE = 1 (AVDD1, 3.3
V), the AD9445 outputs are LVDS compatible, and the pin
assignment for the device is as defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.
RF ENABLE
The RF ENABLE pin is a CMOS-compatible control pin that
optimizes the configuration of the AD9445 analog front end.
The crossover analog input frequency for determining the
RF ENABLE connection differs for the 105 MSPS and 125 MSPS
speed grades. For the 125 MSPS speed grade, connecting the
RF ENABLE to AGND optimizes SFDR performance for appli-
cations with analog input frequencies <210 MHz. For applications
with analog inputs >210 MHz, this pin should be connected to
AVDD1 for optimum SFDR performance. Connecting this pin to
AVDD1 reconfigures the ADC, thereby improving high IF and RF
spurious performance. Operating in this mode increases power dis-
sipation from AVDD2 by 150 mW to 200 mW For the 105 MSPS
speed grade, connecting RF ENABLE to AGND optimizes SFDR
performance for applications with analog input frequencies
<230 MHz. For applications with analog inputs >230 MHz, this
pin should be connected to AVDD1 to optimize performance.
Table 10. Digital Output Coding
VIN+ VIN
Input Span = 3.2 V p-p (V)
16,383 +1.600
8192
0
8191
0.000195
0
1.60
Code
VIN+ VIN
Input Span = 2 V p-p (V)
+1.000
0
0.000122
1.00
Digital Output
Offset Binary (D13D0)
11 1111 1111 1111
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0000
Digital Output
Twos Complement (D13D0)
01 1111 1111 1111
00 0000 0000 0000
11 1111 1111 1111
10 0000 0000 0000
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9445BSV-105 制造商:Analog Devices 功能描述:ADC SGL PIPELINED 105MSPS 14BIT PARALLEL 100TQFP EP - Bulk
AD9445BSVZ-105 功能描述:IC ADC 14BIT 105MSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極
AD9445BSVZ-125 功能描述:IC ADC 14BIT 125MSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極
AD9445-IF-LVDS 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 105/125 MSPS, IF Sampling ADC
AD9445-IF-LVDS/PCB 制造商:Analog Devices 功能描述:Evaluation Kit For 14-Bit, 105/125 MAPA, IF Sampling ADC 制造商:Analog Devices 功能描述:EVAL KIT FOR 14BIT, 105/125 MSPS, IF SAMPLING ADC - Bulk
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