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| 型號： | AD8067ART-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | High Gain Bandwidth Product Precision Fast FET⑩ Op Amp |
| 中文描述： | OP-AMP, 1000 uV OFFSET-MAX, PDSO5 |
| 封裝： | PLASTIC, MO-178AA, SOT-23, 5 PIN |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 873K |
| 代理商： | AD8067ART-REEL7 |
AD8067
Input Protection
Rev. 0 | Page 18 of 24
Layout, Grounding, and Bypassing
Considerations
The inputs of the AD8067 are protected with back-to-back diodes
between the input terminals as well as ESD diodes to either power
supply. The result is an input stage with picoamp level input
currents that can withstand 2 kV ESD events (human body model)
with no degradation.
LAYOUT
In extremely low input bias current amplifier applications, stray
leakage current paths must be kept to a minimum. Any voltage
differential between the amplifier inputs and nearby traces will set
up a leakage path through the PCB. Consider a 1 V signal and
100G
to ground present at the input of the amplifier. The resultant
leakage current is 10 pA; this is ten times the input bias current of
the amplifier. Poor PCB layout, contamination, and the board
material can create large leakage currents. Common contaminants
on boards are skin oils, moisture, solder flux, and cleaning agents.
Therefore, it is imperative that the board be thoroughly cleaned and
the board surface be free of contaminants to fully take advantage of
the AD8067’s low input bias currents.
Excessive power dissipation through the protection devices will
destroy or degrade the performance of the amplifier. Differential
voltages greater than 0.7 V will result in an input current of
approximately (|
V
+
–
V
–
| – 0.7
V
)/(
R
I
+
R
G
)), where
R
I
and
R
G
are
the resistors (see Figure 46). For input voltages beyond the positive
supply, the input current will be about (
V
I
–
V
CC
– 0.7
V
)/
R
I
. For
input voltages beyond the negative supply, the input current will be
about (
V
I
–
V
EE
+ 0.7
V
)/
R
I
. For any of these conditions,
R
I
should
be sized to limit the resulting input current to 50 mA or less.
V
I
R
I
> (V
I
– V
EE
+ 0.7V)/50mA
R
> (V
I
– V
– 0.7V)/50mA
FOR V
BEYOND
SUPPLY VOLTAGES
V
OUT
–
+
R
G
R
F
R
I
–
+
AD8067
R
> ( |V+ – V– | –0.7V)/50mA
FOR LARGE |V+ – V– |
To significantly reduce leakage paths, a guard ring/shield around
the inputs should be used. The guard ring circles the input pins and
is driven to the same potential as the input signal, thereby reducing
the potential difference between pins. For the guard ring to be com-
pletely effective, it must be driven by a relatively low impedance
source and should completely surround the input leads on all sides,
above, and below, using a multilayer board (see Figure 47). The
SOT-23-5 package presents a challenge in keeping the leakage paths
to a minimum. The pin spacing is very tight, so extra care must be
used when constructing the guard ring (see Figure 48 for
recommended guard-ring construction).
Figure 46. Current Limiting Resistor
Capacitive Load Drive
Capacitive load introduces a pole in the amplifier loop response
due to the finite output impedance of the amplifier. This can cause
excessive peaking and ringing in the response. The AD8067 with a
gain of +10 will handle up to a 30 pF capacitive load without an
excessive amount of peaking (see Figure 8). If greater capacitive
load drive is required, consider inserting a small resistor in series
with the load (24.9
is a good value to start with). Capacitive load
drive capability also increases as the gain of the amplifier increases.
NON-INVERTING
GUARD RING
INVERTING
GUARD RING
Figure 47. Guard-Ring Configurations
+V
–IN
+IN
–V
V
OUT
AD8067
NONINVERTING
+V
–IN
+IN
–V
V
OUT
AD8067
INVERTING
Figure 48. Guard-Ring Layout SOT-23-5
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